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preliminary 132 rgb source & 176 gate driver with internal gram for 65,536 colors tft-lcd july 9, 2002 ver. 0 . 4 prepared by: goohyung chung kuku81@samsung.co.kr contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team. s6d 0 110 11
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 2 s6 d 0110 specification revision history version content author date 0 .0 original g. h. jung march 16 , 2002 0 . 1 modified descriptions for operating voltage. (page 4) modified figure for pad configuration. (page 6) added descriptions for im2-0 pin mode setting. (page 10) added descriptions for /rd pin. (page 10) modified table for register selection. (page 12) added table for gram address. (page 17-18) modified table for instruction. (page 20) modified descriptions for r00h. (page 22) added descriptions for sm bit in r01h. (page 23) modified descriptions for bt2-0 bits in r03h. (page 26) modified descriptions for cad bit in r04h. (page 28) modified descriptions for vdv4-0 bits in r0eh. (page 30) added descriptions for r08h, r09h. (page 36) modified figure for window address setting range. (page 41) modified table for gram data and grayscale level. (page 43) modified figure for voltage regulation function. (page 47) added descriptions and table for system interface.(page 48) modified figure for high-speed ram write in window address range. (page 56) added descriptions and figure for gate driver scan mode setting. (page 69) modified figure for setup procedure of 8color display mode.(page 83) modified figure for instruction setup flow. (page 85-86) modified figure for interlaced drive. (page 89) modified descriptions for restriction on the 1 st /2 nd screen driving position register setting. (page 93) m. s. song april 1 , 2002 0.2 modified descriptions for introduction. (page 3) modified descriptions for features. (page 4) modified figure for block diagram. (page 5) modified figure for pad configuration. (page 6) added table for pad dimension. (page 7) added figure for align key configuration and its coordinate. (page 8-9) added table for pad center coordinates. (page 10-13) modified and added descriptions for pin description. (page 14-18) modified descriptions for power supply circuit. (page 21) modified figure for voltage setting. (page 22) added figure for application circuit. (page 102) m. s. song april 12 , 2002 0.3 modified table for pad dimension. (page 7) added table for blanking period setting. (page 43) modified descriptions for reset function. (page 53) m. s. song april 30 , 2002 0.4 modified descriptions for vc2-0 and vrl3-0 bit. (page 36) added descriptions and table contents for bgr bit. (page 39-40) m. s. song july 9, 2002
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 3 introduction the S6D0110 is 1-chip solution for tft-lcd panel: source driver with built-in memory, gate driver, power ic are integrated on one chip. this ic can display to a maximum of 132-rgb x 176-dot graphics on 65k-color tft panel. the S6D0110 also supports bit-operation functions, 8/16-bit high-speed bus interface, and high-speed ram-write functions enable efficient data transfer and high-speed rewriting of data to the internal gram. the moving picture area can be specified in internal gram by window function. the specified window area can be updated selectively so that moving picture is able to displayed simultaneously independent of still picture area. the S6D0110 has various functions for reducing the power consumption of a lcd system: it operates at low voltage (minimum 1.8v) and the ic has an internal gram to store 132- rgb x 176 -dot 65k-color image. in addition, it has the internal booster that generates the lcd driving voltage, b r eeder resistance and the voltage follower circuit for lcd driver. this lsi is suitable for any medium-sized or small portable mobile solution requiring long-term driving capabilities, such as digital cellular phones supporting a web browser, bi - directional pagers, and small pdas.
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 4 features 132 - rgb x 176 -dot tft- lcd display controller/driver ic for 65 ,536 colors ( 396ch-source driver/176ch-gate driver) 16-/8-bit high-speed bus interface and serial peripheral interface ( spi) high-speed burst-ram write function writing to a window-ram address area by using a window-address function bit-operation functions for graphic processing - write-data mask functions in bit unit s - logical operation in pixel unit and conditional write function various color-display control functions - 65,536 colors can be displayed at the same time (gamma adjust included) - vertical scroll display function in raster-row units internal ram capacity: 132 x 16 x 176 = 371,712 b it s low -power operati on su pports : - power-save functions such as the standby mode and sleep mode - partial lcd drive of two screens in any position - maximum 12-times step-up circuit for liquid crystal drive voltage - voltage followers to decrease direct current flow in the lcd drive breeder-resistors - equalizing function for the switching performance of step-up circuits and operational amplifiers n -raster row inversion drive ( r everse the polar ity of driving voltage in every selected raster row is possible) internal oscillation and hardware reset structure for tft-display retention volume (cst/cadd structure) alternating functions for tft-display counter-electrode power supply - n-line alternating drive of vcom (vgoff is also available for n-line alternating drive for cadd) internal p ower supply ci rcuit - step-up circuit: five to nine times, positive-polarity inversion - adjustment of vcom(vgoff) amplitude: internal 22-level digital potentiometer o perati ng voltage applying voltage - vdd to vss = 1. 8 to 2.5 v (non-regulating) (logic voltage ra nge ? non-regulated ) vdd3 to vss = 2.3 to 3.3 v (regulating) (logic voltage range ? regulated) - v ci to vss = 2.5 to 3.3 v ( internal reference power-supply volt age) - vci1 to vss = 1.7 to 2.75 v (2.5 x 0.68 ~ 2.75) (power supply for step-up circuits) generating voltage - for the source driver: avdd to vss = 3.5 to 5.5v (power supply for liquid crystal output circuits) gvdd to vss = 3.0 to 5.0v (reference power supply for grayscale voltages) - for the gate driver: vgh to vgl = 14 to 30 v, vgh to vss = +7.0 to +20 v, vgoffl = (vgl+0.5) to ? 7.5v, vgoffh = ~ to -1.5v - for the tft-display counter electrode: vcom amplitude(max) = 6v, vcomh to vss(max) = gvdd vcoml to vss(max) = 1.0 v to -vci + 0.5 v
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 5 block diagram 396 ch. source driver built-in gram 132x16x176 = 371,712 bits osc system interface 8-/16-bit parallel, 3-pin spi 178 ch. gate driver vgh vgl vgoff vdd3 vss timing generator write data latch control register s1 s2 s3 : : : : s394 s395 s396 m/ac circuit latch circuit grayscale voltage generator gamma adjusting circuit built-in power supply circuit g0 g1 g2 : : g175 g176 g177 address counter read data latch bit operation index register gate control / 64 / 64 / 16 / 16 / 16 / 64 vci cl1 m flm eq disptmg osc1 osc2 power regulator gvdd avdd vci1/2/3/4 vbs vgs cgnd avss vcl vreg1 vreg1out vreg2 vreg2out regp/regn vcomh/l/r vcomout vgoffh/l vgoffout resetb im[2:0] cs rs e rw db[15:2] db1/sdo db0/sdi pregb rdvdd vdd3 vdd / 2 / 3 / 2 figure 1 . block diagram
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 6 pad configuration S6D0110 g109 g111 g113 g169 g171 g173 g175 s1 s2 s3 s4 x y (0,0) dummy2 s393 s394 s395 s396 contact1 contact2 vcomout dummy1 dummy4 resetb1 dummy3 g107 g0 g1 g3 g5 g7 g105 g103 g101 g99 g9 g115 g117 g119 g121 g167 g165 g163 g161 dummy45 s5 s6 s7 s8 g177 g176 g174 g172 g170 dummy29 g168 g166 g164 s392 s391 s390 s389 dummy59 dummy56 dummy53 g108 g110 g112 g114 vgh vgh vci3 c23+ c23+ c23- c23- c22+ c22+ c22- c21+ c21+ c21- c21- c41+ c41+ c41- c41- c31+ c31+ c31- c31- vgl vgl vgl vgl c22- vdd3o im0/id vsso im1 vdd3o im2 vdd3o pregb vdd3o resetb2 dummy6 vsso cgnd cgnd cgnd db15 db14 db13 db12 db11 db10 db9 db8 dummy9 dummy7 dummy8 db7 db6 db5 db4 db3 db2 db1/sdo db0/sdi vsso vsso rd wr/scl rs cs dummy10 avss vsso dummy11 vsso avss avss avss avss avss avss avss vss vss vss vss vss rdvdd rdvdd rdvdd rdvdd vdd vdd vci vci4 osc1 vdd vdd vbs vci vci vci vci osc2 vdd3o vdd3 vdd3 vdd3 cl1 m flm eq disptmg test vgs vgs vgs vgs vgs vgs vsso vss vss vss vss vss vss vcoml vcomh vcl vcl vci1 vci1 vci1 dummy12 dummy13 vcomr vreg1out vreg1 gvdd gvdd vci1 vss vss vss regp regn vci2 avdd avdd vci3 c11- c11- c11- c11- c11+ c11+ c11+ c11+ c12- c12- c12- c12- c12+ c12+ c12+ c12+ vgoff vgoffout vgoffh vgoffl vreg2out dummy14 vcomout resetb3 vreg2 dummy20 g116 g118 g120 g122 g124 g2 g4 g6 g8 g10 g104 g106 g102 g100 dummy26 dummy22 dummy21 dummy23 dummy5 g97 g98 vcomout vci3 vcoml vci3 vgoff vgoffout vgoffh vgoffl vreg2 vreg2out dummy15 dummy16 dummy17 dummy18 dummy19 vcomout dummy24 dummy25 dummy27 dummy28 dummy30 dummy31 dummy32 dummy33 dummy34 dummy35 dummy36 dummy46 dummy47 dummy48 dummy49 dummy50 dummy51 dummy52 dummy54 dummy55 dummy57 dummy58 dummy60 2980 um 19700 um gvdd gvdd figure 2 . pad configuration
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 7 table 1 . s6 d0110 pad dimensions size items pad name . x y unit chip size 1) - 19580 2860 input pad 54 100 pad size output pad 36 70 u m notes: 1. scribe line is not included in this chip size (scribe line: 120um)
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 8 align k ey configuration and c oordinate left cog align key right cog align key 30 um 40 um 30 um 30 um 40 um 30 um (-9512, -1315) 190 um 190 um 45 um 45 um 45 um 45 um 30 um 40 um 30 um 30 um 40 um 30 um (9512, -1315) 190 um 190 um 45 um 45 um 45 um 45 um 100 120 29 9 37 76 110 (9699, 1341) 120 100 29 9 37 76 110 (-9699, -1227) left ilb align key right ilb align key figure 3 . cog and ilb align key
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 9 metal size 45um 45um 45um 45um bump size 55um 55um 55um 55um (-9694,1205) cog key bump key ilb key cog key ilb key figure 4 . bump align key and align key configuration notes: 2. gold bump height: 15um(typ.) 2. wafer thickness: 470um
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 10 pad center coordinates table 2 . p ad center coordinates [unit: um ] no. pad name x y no. pad name x y no. pad name x y no. pad name x y 1 dummy<1> -9360 -1356 61 db<11> -3200 -1356 121 eq 1600 -1356 181 vgoff 6400 -1356 2 vcomout -9280 -1356 62 db<10> -3120 -1356 122 disptmg 1680 -1356 182 vgoffout 6480 -1356 3 vcomout -9200 -1356 63 db<9> -3040 -1356 123 test 1760 -1356 183 vgoffout 6560 -1356 4 contact1 -9120 -1356 64 db<8> -2960 -1356 124 vgs 1840 -1356 184 vgoffh 6640 -1356 5 contact2 -9040 -1356 65 dummy<9> -2880 -1356 125 vgs 1920 -1356 185 vgoffh 6720 -1356 6 resetb1 -8960 -1356 66 vsso -2800 -1356 126 vgs 2000 -1356 186 vgoffl 6800 -1356 7 dummy<2> -8880 -1356 67 db<7> -2720 -1356 127 vgs 2080 -1356 187 vgoffl 6880 -1356 8 dummy<3> -8280 -1356 68 db<6> -2640 -1356 128 vgs 2160 -1356 188 vreg2 6960 -1356 9 dummy<4> -7780 -1356 69 db<5> -2560 -1356 129 vgs 2240 -1356 189 vreg2 7040 -1356 10 dummy<5> -7280 -1356 70 db<4> -2480 -1356 130 vss 2320 -1356 190 vreg2out 7120 -1356 11 vgh -7200 -1356 71 db<3> -2400 -1356 131 vss 2400 -1356 191 vreg2out 7200 -1356 12 vgh -7120 -1356 72 db<2> -2320 -1356 132 vss 2480 -1356 192 dummy<14> 7280 -1356 13 vci3 -7040 -1356 73 db1/sdo -2240 -1356 133 vss 2560 -1356 193 dummy<15> 7780 -1356 14 vci3 -6960 -1356 74 db0/sdi -2160 -1356 134 vss 2640 -1356 194 dummy<16> 8280 -1356 15 c23+ -6880 -1356 75 dummy<10> -2080 -1356 135 vss 2720 -1356 195 dummy<17> 8880 -1356 16 c23+ -6800 -1356 76 vsso -2000 -1356 136 vss 2800 -1356 196 resetb3 8960 -1356 17 c23- -6720 -1356 77 r/w -1920 -1356 137 vss 2880 -1356 197 dummy<18> 9040 -1356 18 c23- -6640 -1356 78 e -1840 -1356 138 vss 2960 -1356 198 dummy<19> 9120 -1356 19 c22+ -6560 -1356 79 rs -1760 -1356 139 vcoml 3040 -1356 199 vcomout 9200 -1356 20 c22+ -6480 -1356 80 csb -1680 -1356 140 vcoml 3120 -1356 200 vcomout 9280 -1356 21 c22- -6400 -1356 81 dummy<11> -1600 -1356 141 dummy<12> 3200 -1356 201 dummy<20> 9360 -1356 22 c22- -6320 -1356 82 vsso -1520 -1356 142 dummy<13> 3280 -1356 202 dummy<21> 9720 -1078 23 c21+ -6240 -1356 83 avss -1440 -1356 143 vcomr 3360 -1356 203 dummy<22> 9610 -1040 24 c21+ -6160 -1356 84 avss -1360 -1356 144 vreg1out 3440 -1356 204 g<2> 9720 -1002 25 c21- -6080 -1356 85 avss -1280 -1356 145 vreg1 3520 -1356 205 g<4> 9610 -964 26 c21- -6000 -1356 86 avss -1200 -1356 146 gvdd 3600 -1356 206 g<6> 9720 -926 27 c41+ -5920 -1356 87 avss -1120 -1356 147 gvdd 3680 -1356 207 g<8> 9610 -888 28 c41+ -5840 -1356 88 avss -1040 -1356 148 gvdd 3760 -1356 208 g<10> 9720 -850 29 c41- -5760 -1356 89 avss -960 -1356 149 gvdd 3840 -1356 209 g<12> 9610 -812 30 c41- -5680 -1356 90 avss -880 -1356 150 vcomh 3920 -1356 210 g<14> 9720 -774 31 c31+ -5600 -1356 91 vss* -800 -1356 151 vcl 4000 -1356 211 g<16> 9610 -736 32 c31+ -5520 -1356 92 vss -720 -1356 152 vcl 4080 -1356 212 g<18> 9720 -698 33 c31- -5440 -1356 93 vss -640 -1356 153 vci1 4160 -1356 213 g<20> 9610 -660 34 c31- -5360 -1356 94 vss -560 -1356 154 vci1 4240 -1356 214 g<22> 9720 -622 35 vgl -5280 -1356 95 vss -480 -1356 155 vci1 4320 -1356 215 g<24> 9610 -584 36 vgl -5200 -1356 96 vss -400 -1356 156 vci1 4400 -1356 216 g<26> 9720 -546 37 vgl -5120 -1356 97 vdd3* -320 -1356 157 regp 4480 -1356 217 g<28> 9610 -508 38 vgl -5040 -1356 98 vdd3 -240 -1356 158 regn 4560 -1356 218 g<30> 9720 -470 39 cgnd -4960 -1356 99 vdd3 -160 -1356 159 vci2 4640 -1356 219 g<32> 9610 -432 40 cgnd -4880 -1356 100 vdd3 -80 -1356 160 avdd 4720 -1356 220 g<34> 9720 -394 41 cgnd -4800 -1356 101 rdvdd 0 -1356 161 avdd 4800 -1356 221 g<36> 9610 -356 42 vdd3o -4720 -1356 102 rdvdd 80 -1356 162 vci3 4880 -1356 222 g<38> 9720 -318 43 im<0> -4640 -1356 103 rdvdd 160 -1356 163 vci3 4960 -1356 223 g<40> 9610 -280 44 vsso -4560 -1356 104 rdvdd 240 -1356 164 c11- 5040 -1356 224 g<42> 9720 -242 45 im<1> -4480 -1356 105 vdd 320 -1356 165 c11- 5120 -1356 225 g<44> 9610 -204 46 vdd3o -4400 -1356 106 vdd 400 -1356 166 c11- 5200 -1356 226 g<46> 9720 -166 47 im<2> -4320 -1356 107 vdd 480 -1356 167 c11- 5280 -1356 227 g<48> 9610 -128 48 vdd3o -4240 -1356 108 vdd 560 -1356 168 c11+ 5360 -1356 228 g<50> 9720 -90 49 dummy<6> -4160 -1356 109 vbs 640 -1356 169 c11+ 5440 -1356 229 g<52> 9610 -52 50 vsso -4080 -1356 110 vci 720 -1356 170 c11+ 5520 -1356 230 g<54> 9720 -14 51 pregb -4000 -1356 111 vci 800 -1356 171 c11+ 5600 -1356 231 g<56> 9610 24 52 vdd3o -3920 -1356 112 vci 880 -1356 172 c12- 5680 -1356 232 g<58> 9720 62 53 resetb2 -3840 -1356 113 vci 960 -1356 173 c12- 5760 -1356 233 g<60> 9610 100 54 vsso -3760 -1356 114 vci 1040 -1356 174 c12- 5840 -1356 234 g<62> 9720 138 55 dummy<7> -3680 -1356 115 vci4 1120 -1356 175 c12- 5920 -1356 235 g<64> 9610 176 56 dummy<8> -3600 -1356 116 osc1 1200 -1356 176 c12+ 6000 -1356 236 g<66> 9720 214 57 db<15> -3520 -1356 117 osc2 1280 -1356 177 c12+ 6080 -1356 237 g<68> 9610 252 58 db<14> -3440 -1356 118 cl1 1360 -1356 178 c12+ 6160 -1356 238 g<70> 9720 290 59 db<13> -3360 -1356 119 m 1440 -1356 179 c12+ 6240 -1356 239 g<72> 9610 328 60 db<12> -3280 -1356 120 flm 1520 -1356 180 vgoff 6320 -1356 240 g<74> 9720 366 notes: no. 91 & 92, no.97 & 98 pad must be short by external wiring.
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 11 table 3 . p ad center coordinates (continued) [unit: um ] no. pad name x y no. pad name x y no. pad name x y no. pad name x y 241 g<76> 9610 404 301 dummy<31> 7914 1362 361 s<342> 5634 1362 421 s<282> 3354 1362 242 g<78> 9720 442 302 dummy<32> 7876 1252 362 s<341> 5596 1252 422 s<281> 3316 1252 243 g<80> 9610 480 303 dummy<33> 7838 1362 363 s<340> 5558 1362 423 s<280> 3278 1362 244 g<82> 9720 518 304 dummy<34> 7800 1252 364 s<339> 5520 1252 424 s<279> 3240 1252 245 g<84> 9610 556 305 dummy<35> 7762 1362 365 s<338> 5482 1362 425 s<278> 3202 1362 246 g<86> 9720 594 306 dummy<36> 7724 1252 366 s<337> 5444 1252 426 s<277> 3164 1252 247 g<88> 9610 632 307 s<396> 7686 1362 367 s<336> 5406 1362 427 s<276> 3126 1362 248 g<90> 9720 670 308 s<395> 7648 1252 368 s<335> 5368 1252 428 s<275> 3088 1252 249 g<92> 9610 708 309 s<394> 7610 1362 369 s<334> 5330 1362 429 s<274> 3050 1362 250 g<94> 9720 746 310 s<393> 7572 1252 370 s<333> 5292 1252 430 s<273> 3012 1252 251 g<96> 9610 784 311 s<392> 7534 1362 371 s<332> 5254 1362 431 s<272> 2974 1362 252 g<98> 9720 822 312 s<391> 7496 1252 372 s<331> 5216 1252 432 s<271> 2936 1252 253 g<100> 9610 860 313 s<390> 7458 1362 373 s<330> 5178 1362 433 s<270> 2898 1362 254 g<102> 9720 898 314 s<389> 7420 1252 374 s<329> 5140 1252 434 s<269> 2860 1252 255 g<104> 9610 936 315 s<388> 7382 1362 375 s<328> 5102 1362 435 s<268> 2822 1362 256 g<106> 9720 974 316 s<387> 7344 1252 376 s<327> 5064 1252 436 s<267> 2784 1252 257 dummy<23> 9610 1012 317 s<386> 7306 1362 377 s<326> 5026 1362 437 s<266> 2746 1362 258 dummy<24> 9720 1050 318 s<385> 7268 1252 378 s<325> 4988 1252 438 s<265> 2708 1252 259 dummy<25> 9610 1088 319 s<384> 7230 1362 379 s<324> 4950 1362 439 s<264> 2670 1362 260 dummy<26> 9472 1252 320 s<383> 7192 1252 380 s<323> 4912 1252 440 s<263> 2632 1252 261 dummy<27> 9434 1362 321 s<382> 7154 1362 381 s<322> 4874 1362 441 s<262> 2594 1362 262 dummy<28> 9396 1252 322 s<381> 7116 1252 382 s<321> 4836 1252 442 s<261> 2556 1252 263 g<108> 9358 1362 323 s<380> 7078 1362 383 s<320> 4798 1362 443 s<260> 2518 1362 264 g<110> 9320 1252 324 s<379> 7040 1252 384 s<319> 4760 1252 444 s<259> 2480 1252 265 g<112> 9282 1362 325 s<378> 7002 1362 385 s<318> 4722 1362 445 s<258> 2442 1362 266 g<114> 9244 1252 326 s<377> 6964 1252 386 s<317> 4684 1252 446 s<257> 2404 1252 267 g<116> 9206 1362 327 s<376> 6926 1362 387 s<316> 4646 1362 447 s<256> 2366 1362 268 g<118> 9168 1252 328 s<375> 6888 1252 388 s<315> 4608 1252 448 s<255> 2328 1252 269 g<120> 9130 1362 329 s<374> 6850 1362 389 s<314> 4570 1362 449 s<254> 2290 1362 270 g<122> 9092 1252 330 s<373> 6812 1252 390 s<313> 4532 1252 450 s<253> 2252 1252 271 g<124> 9054 1362 331 s<372> 6774 1362 391 s<312> 4494 1362 451 s<252> 2214 1362 272 g<126> 9016 1252 332 s<371> 6736 1252 392 s<311> 4456 1252 452 s<251> 2176 1252 273 g<128> 8978 1362 333 s<370> 6698 1362 393 s<310> 4418 1362 453 s<250> 2138 1362 274 g<130> 8940 1252 334 s<369> 6660 1252 394 s<309> 4380 1252 454 s<249> 2100 1252 275 g<132> 8902 1362 335 s<368> 6622 1362 395 s<308> 4342 1362 455 s<248> 2062 1362 276 g<134> 8864 1252 336 s<367> 6584 1252 396 s<307> 4304 1252 456 s<247> 2024 1252 277 g<136> 8826 1362 337 s<366> 6546 1362 397 s<306> 4266 1362 457 s<246> 1986 1362 278 g<138> 8788 1252 338 s<365> 6508 1252 398 s<305> 4228 1252 458 s<245> 1948 1252 279 g<140> 8750 1362 339 s<364> 6470 1362 399 s<304> 4190 1362 459 s<244> 1910 1362 280 g<142> 8712 1252 340 s<363> 6432 1252 400 s<303> 4152 1252 460 s<243> 1872 1252 281 g<144> 8674 1362 341 s<362> 6394 1362 401 s<302> 4114 1362 461 s<242> 1834 1362 282 g<146> 8636 1252 342 s<361> 6356 1252 402 s<301> 4076 1252 462 s<241> 1796 1252 283 g<148> 8598 1362 343 s<360> 6318 1362 403 s<300> 4038 1362 463 s<240> 1758 1362 284 g<150> 8560 1252 344 s<359> 6280 1252 404 s<299> 4000 1252 464 s<239> 1720 1252 285 g<152> 8522 1362 345 s<358> 6242 1362 405 s<298> 3962 1362 465 s<238> 1682 1362 286 g<154> 8484 1252 346 s<357> 6204 1252 406 s<297> 3924 1252 466 s<237> 1644 1252 287 g<156> 8446 1362 347 s<356> 6166 1362 407 s<296> 3886 1362 467 s<236> 1606 1362 288 g<158> 8408 1252 348 s<355> 6128 1252 408 s<295> 3848 1252 468 s<235> 1568 1252 289 g<160> 8370 1362 349 s<354> 6090 1362 409 s<294> 3810 1362 469 s<234> 1530 1362 290 g<162> 8332 1252 350 s<353> 6052 1252 410 s<293> 3772 1252 470 s<233> 1492 1252 291 g<164> 8294 1362 351 s<352> 6014 1362 411 s<292> 3734 1362 471 s<232> 1454 1362 292 g<166> 8256 1252 352 s<351> 5976 1252 412 s<291> 3696 1252 472 s<231> 1416 1252 293 g<168> 8218 1362 353 s<350> 5938 1362 413 s<290> 3658 1362 473 s<230> 1378 1362 294 g<170> 8180 1252 354 s<349> 5900 1252 414 s<289> 3620 1252 474 s<229> 1340 1252 295 g<172> 8142 1362 355 s<348> 5862 1362 415 s<288> 3582 1362 475 s<228> 1302 1362 296 g<174> 8104 1252 356 s<347> 5824 1252 416 s<287> 3544 1252 476 s<227> 1264 1252 297 g<176> 8066 1362 357 s<346> 5786 1362 417 s<286> 3506 1362 477 s<226> 1226 1362 298 g<177> 8028 1252 358 s<345> 5748 1252 418 s<285> 3468 1252 478 s<225> 1188 1252 299 dummy<29> 7990 1362 359 s<344> 5710 1362 419 s<284> 3430 1362 479 s<224> 1150 1362 300 dummy<30> 7952 1252 360 s<343> 5672 1252 420 s<283> 3392 1252 480 s<223> 1112 1252
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 12 table 4 . p ad center coordinates (continued) [unit: um ] no. pad name x y no. pad name x y no. pad name x y no. pad name x y 481 s<222> 1074 1362 541 s<170> -1206 1362 601 s<110> -3486 1362 661 s<50> -5766 1362 482 s<221> 1036 1252 542 s<169> -1244 1252 602 s<109> -3524 1252 662 s<49> -5804 1252 483 s<220> 998 1362 543 s<168> -1282 1362 603 s<108> -3562 1362 663 s<48> -5842 1362 484 s<219> 960 1252 544 s<167> -1320 1252 604 s<107> -3600 1252 664 s<47> -5880 1252 485 s<218> 922 1362 545 s<166> -1358 1362 605 s<106> -3638 1362 665 s<46> -5918 1362 486 s<217> 884 1252 546 s<165> -1396 1252 606 s<105> -3676 1252 666 s<45> -5956 1252 487 s<216> 846 1362 547 s<164> -1434 1362 607 s<104> -3714 1362 667 s<44> -5994 1362 488 s<215> 808 1252 548 s<163> -1472 1252 608 s<103> -3752 1252 668 s<43> -6032 1252 489 s<214> 770 1362 549 s<162> -1510 1362 609 s<102> -3790 1362 669 s<42> -6070 1362 490 s<213> 732 1252 550 s<161> -1548 1252 610 s<101> -3828 1252 670 s<41> -6108 1252 491 s<212> 694 1362 551 s<160> -1586 1362 611 s<100> -3866 1362 671 s<40> -6146 1362 492 s<211> 656 1252 552 s<159> -1624 1252 612 s<99> -3904 1252 672 s<39> -6184 1252 493 s<210> 618 1362 553 s<158> -1662 1362 613 s<98> -3942 1362 673 s<38> -6222 1362 494 s<209> 580 1252 554 s<157> -1700 1252 614 s<97> -3980 1252 674 s<37> -6260 1252 495 s<208> 542 1362 555 s<156> -1738 1362 615 s<96> -4018 1362 675 s<36> -6298 1362 496 s<207> 504 1252 556 s<155> -1776 1252 616 s<95> -4056 1252 676 s<35> -6336 1252 497 s<206> 466 1362 557 s<154> -1814 1362 617 s<94> -4094 1362 677 s<34> -6374 1362 498 s<205> 428 1252 558 s<153> -1852 1252 618 s<93> -4132 1252 678 s<33> -6412 1252 499 s<204> 390 1362 559 s<152> -1890 1362 619 s<92> -4170 1362 679 s<32> -6450 1362 500 s<203> 352 1252 560 s<151> -1928 1252 620 s<91> -4208 1252 680 s<31> -6488 1252 501 s<202> 314 1362 561 s<150> -1966 1362 621 s<90> -4246 1362 681 s<30> -6526 1362 502 s<201> 276 1252 562 s<149> -2004 1252 622 s<89> -4284 1252 682 s<29> -6564 1252 503 s<200> 238 1362 563 s<148> -2042 1362 623 s<88> -4322 1362 683 s<28> -6602 1362 504 s<199> 200 1252 564 s<147> -2080 1252 624 s<87> -4360 1252 684 s<27> -6640 1252 505 s<198> 162 1362 565 s<146> -2118 1362 625 s<86> -4398 1362 685 s<26> -6678 1362 506 s<197> 124 1252 566 s<145> -2156 1252 626 s<85> -4436 1252 686 s<25> -6716 1252 507 s<196> 86 1362 567 s<144> -2194 1362 627 s<84> -4474 1362 687 s<24> -6754 1362 508 s<195> 48 1252 568 s<143> -2232 1252 628 s<83> -4512 1252 688 s<23> -6792 1252 509 s<194> 10 1362 569 s<142> -2270 1362 629 s<82> -4550 1362 689 s<22> -6830 1362 510 s<193> -28 1252 570 s<141> -2308 1252 630 s<81> -4588 1252 690 s<21> -6868 1252 511 dummy<37> -66 1362 571 s<140> -2346 1362 631 s<80> -4626 1362 691 s<20> -6906 1362 512 dummy<38> -104 1252 572 s<139> -2384 1252 632 s<79> -4664 1252 692 s<19> -6944 1252 513 dummy<39> -142 1362 573 s<138> -2422 1362 633 s<78> -4702 1362 693 s<18> -6982 1362 514 dummy<40> -180 1252 574 s<137> -2460 1252 634 s<77> -4740 1252 694 s<17> -7020 1252 515 dummy<41> -218 1362 575 s<136> -2498 1362 635 s<76> -4778 1362 695 s<16> -7058 1362 516 dummy<42> -256 1252 576 s<135> -2536 1252 636 s<75> -4816 1252 696 s<15> -7096 1252 517 dummy<43> -294 1362 577 s<134> -2574 1362 637 s<74> -4854 1362 697 s<14> -7134 1362 518 dummy<44> -332 1252 578 s<133> -2612 1252 638 s<73> -4892 1252 698 s<13> -7172 1252 519 s<192> -370 1362 579 s<132> -2650 1362 639 s<72> -4930 1362 699 s<12> -7210 1362 520 s<191> -408 1252 580 s<131> -2688 1252 640 s<71> -4968 1252 700 s<11> -7248 1252 521 s<190> -446 1362 581 s<130> -2726 1362 641 s<70> -5006 1362 701 s<10> -7286 1362 522 s<189> -484 1252 582 s<129> -2764 1252 642 s<69> -5044 1252 702 s<9> -7324 1252 523 s<188> -522 1362 583 s<128> -2802 1362 643 s<68> -5082 1362 703 s<8> -7362 1362 524 s<187> -560 1252 584 s<127> -2840 1252 644 s<67> -5120 1252 704 s<7> -7400 1252 525 s<186> -598 1362 585 s<126> -2878 1362 645 s<66> -5158 1362 705 s<6> -7438 1362 526 s<185> -636 1252 586 s<125> -2916 1252 646 s<65> -5196 1252 706 s<5> -7476 1252 527 s<184> -674 1362 587 s<124> -2954 1362 647 s<64> -5234 1362 707 s<4> -7514 1362 528 s<183> -712 1252 588 s<123> -2992 1252 648 s<63> -5272 1252 708 s<3> -7552 1252 529 s<182> -750 1362 589 s<122> -3030 1362 649 s<62> -5310 1362 709 s<2> -7590 1362 530 s<181> -788 1252 590 s<121> -3068 1252 650 s<61> -5348 1252 710 s<1> -7628 1252 531 s<180> -826 1362 591 s<120> -3106 1362 651 s<60> -5386 1362 711 dummy<45> -7666 1362 532 s<179> -864 1252 592 s<119> -3144 1252 652 s<59> -5424 1252 712 dummy<46> -7704 1252 533 s<178> -902 1362 593 s<118> -3182 1362 653 s<58> -5462 1362 713 dummy<47> -7742 1362 534 s<177> -940 1252 594 s<117> -3220 1252 654 s<57> -5500 1252 714 dummy<48> -7780 1252 535 s<176> -978 1362 595 s<116> -3258 1362 655 s<56> -5538 1362 715 dummy<49> -7818 1362 536 s<175> -1016 1252 596 s<115> -3296 1252 656 s<55> -5576 1252 716 dummy<50> -7856 1252 537 s<174> -1054 1362 597 s<114> -3334 1362 657 s<54> -5614 1362 717 dummy<51> -7894 1362 538 s<173> -1092 1252 598 s<113> -3372 1252 658 s<53> -5652 1252 718 dummy<52> -7932 1252 539 s<172> -1130 1362 599 s<112> -3410 1362 659 s<52> -5690 1362 719 g<175> -7970 1362 540 s<171> -1168 1252 600 s<111> -3448 1252 660 s<51> -5728 1252 720 g<173> -8008 1252
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 13 table 5 . p ad center coordinates (continued) [unit: um ] no. pad name x y no. pad name x y no. pad name x y no. pad name x y 721 g<171> -8046 1362 781 g<63> -9720 176 722 g<169> -8084 1252 782 g<61> -9610 138 723 g<167> -8122 1362 783 g<59> -9720 100 724 g<165> -8160 1252 784 g<57> -9610 62 725 g<163> -8198 1362 785 g<55> -9720 24 726 g<161> -8236 1252 786 g<53> -9610 -14 727 g<159> -8274 1362 787 g<51> -9720 -52 728 g<157> -8312 1252 788 g<49> -9610 -90 729 g<155> -8350 1362 789 g<47> -9720 -128 730 g<153> -8388 1252 790 g<45> -9610 -166 731 g<151> -8426 1362 791 g<43> -9720 -204 732 g<149> -8464 1252 792 g<41> -9610 -242 733 g<147> -8502 1362 793 g<39> -9720 -280 734 g<145> -8540 1252 794 g<37> -9610 -318 735 g<143> -8578 1362 795 g<35> -9720 -356 736 g<141> -8616 1252 796 g<33> -9610 -394 737 g<139> -8654 1362 797 g<31> -9720 -432 738 g<137> -8692 1252 798 g<29> -9610 -470 739 g<135> -8730 1362 799 g<27> -9720 -508 740 g<133> -8768 1252 800 g<25> -9610 -546 741 g<131> -8806 1362 801 g<23> -9720 -584 742 g<129> -8844 1252 802 g<21> -9610 -622 743 g<127> -8882 1362 803 g<19> -9720 -660 744 g<125> -8920 1252 804 g<17> -9610 -698 745 g<123> -8958 1362 805 g<15> -9720 -736 746 g<121> -8996 1252 806 g<13> -9610 -774 747 g<119> -9034 1362 807 g<11> -9720 -812 748 g<117> -9072 1252 808 g<9> -9610 -850 749 g<115> -9110 1362 809 g<7> -9720 -888 750 g<113> -9148 1252 810 g<5> -9610 -926 751 g<111> -9186 1362 811 g<3> -9720 -964 752 g<109> -9224 1252 812 g<1> -9610 -1002 753 g<107> -9262 1362 813 g<0> -9720 -1040 754 dummy<53> -9300 1252 814 dummy<59> -9610 -1078 755 dummy<54> -9338 1362 815 dummy<60> -9720 -1116 756 dummy<55> -9376 1252 757 dummy<56> -9720 1088 758 dummy<57> -9610 1050 759 dummy<58> -9720 1012 760 g<105> -9610 974 761 g<103> -9720 936 762 g<101> -9610 898 763 g<99> -9720 860 764 g<97> -9610 822 765 g<95> -9720 784 766 g<93> -9610 746 767 g<91> -9720 708 768 g<89> -9610 670 769 g<87> -9720 632 770 g<85> -9610 594 771 g<83> -9720 556 772 g<81> -9610 518 773 g<79> -9720 480 774 g<77> -9610 442 775 g<75> -9720 404 776 g<73> -9610 366 777 g<71> -9720 328 778 g<69> -9610 290 779 g<67> -9720 252 780 g<65> -9610 214
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 14 pin description table 6 . power supply pin description symbol i/o description vdd power system power supply. as S6D0110 have internal regulator, vdd range varies with each mode. non-regulated(pregb = 1) : +1.8 ~ + 2 . 5 v regulated (pregb = 0) : +1.9v vdd3 power system power supply for internal regulator as external power. ( v dd3 : + 2 . 5 to + 3.3 v ) vss power system ground(0v) cgnd power system ground level for step up circuit block. avss power system ground level for analog circuit block. vci power an internal reference power supply for v reg 1out/v reg 2out . connect vdd when vdd = 2.5 to 3.3 v. connect a 2.5 to 3.3 v external-voltage power supply when v dd = 1.8 to 2.5 v. avdd o a power output pin for source driver that is generated from power block. connect a capacitor for stabilization. (avdd: 3.5 to 5.5 v) interconnect this pin to vci2 pin. gvdd o a s tandard level for grayscale voltage generator . connect a capacitor for stabilization. vgs i reference voltage for grayscale voltage generator. vci1 i a reference voltage for step-up circuit 1. vci2 i a reference voltage for step-up circuit 2. vci3 i a reference voltage in step-up circuit 3. vci4 i a reference voltage in step-up circuit 4. connect v ci , v dd , or an external power supply lower than 3.3 v. vcl o a power supply pin for generating vcoml. when vcoml is higher than vss, outputs vss level.
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 15 table 7 . power supply pin description ( continued) symbol i/o description vbs i reference voltage for step-up circuit3. when vgh (max) = 20v, connect this pin to vci. when vgh (max) = 15v, connect this pin to vss. regn, regp i/o input pins for reference voltages of vreg1out, and vreg2out when the internal reference-voltage generation circuit is not used. leave these pins open when the internal reference-voltage generation circuit is used. vreg1out o this pin outputs a reference voltage for vreg1 between avdd( ddvdh ) and vss . when the internal reference voltage is not used, the reference voltage can be generated from the voltage of regp. connect this pin to vreg1 and a capacitor for stabilization. when this pin is not used, leave it open. vreg2out o this pin outputs a reference voltage for vreg2 between vss and vgl when the internal reference voltage is not used, the reference voltage can be generated from the voltage of regn. connect this pin to vreg2 and a capacitor for stabilizatio 0 n. when this pin is not used, leave it open. vcomout o a power supply for the tft-display counter electrode. the alternating cycle can be set by the m pin. connect this pin to the tft-display counter electrode. this pin is also used as equalizing function: when eq = ? high ? period, a ll source driver ? s outputs (s1 to s396) are short to vcom level (hi- z ). in case of vcoml < 0v , equalizing function must not be used. (set eq bit (r07h) to be ? 00 ? for preventing the abnormal function.) vcomr i a reference voltage of vcomh. when vcomh is externally adjusted, halt the internal adjuster of vcomh by setting the register and insert a variable resistor between gvdd and vss . when this pin is not externally adjusted, leave it open and adjust vcomh by setting the internal register. vcomh o this pin indicates a high level of vcom generated in driving the vcom alternation. connect this pin to the capacitor for stabilization. vcoml o when the vcom alternation is driven, this pin indicates a low level of vcom. an internal register can be used to adjust the voltage. connect this pin to a capacitor for stabilization. when the v com g bit is low, the vcoml output stops and a capacitor for stabilization is not needed. vgh o a positive power output pin for gate driver, internal step-up circuits, bias circuits, and operational amplifiers. connect a capacitor for stabilization. interconnect this pin to vci3 pin. vgl o a negative power output pin for gate driver , bias circuits, and operational amplifiers. connect a capacitor for stabilization. when internal vgl generator is not used, connect an external-voltage power supply higher than -1 5 . 0 v.
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 16 table 8 . power supply pin description ( continued) symbol i/o description vgoff i power supply pin for off level for gate of tft. connect this pin to v goffout . vgoffout o an power output pin for gate driver. this pin is a negative voltage for the gate off level. alternation can be synchronized by m pin . set the internal register according to the structure of the tft-display retention volume. for the amplitude at the alternation driving, this pin outputs a voltage between vcomh and vcoml with the vgoffl reference voltage.. vgoffh o when the vgoff alternation is driven, this pin indicates a high level of vgoff. connect a capacitor for stabilization. when the cad bit is low, the vgoffh output stops and a capacitor for stabilization is not needed. vgoffl o when the vgoff alternation is driven, this pin indicates a low level of vgoff. connect a capacitor for stabilization. an internal register can be used to adjust the voltage. c11+,c11- to c23+,c23- - connect the step-up capacitor according to the step-up factor. c31+, c31- - connect a step-up capacitor for generating the vgl level . c41+, c41- - connect a step-up capacitor for generating the - v cl level .
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 17 table 9 . system interface pin description symbol i/o description selects the mpu interface mode: im2 im1 im0/id mpu interface mode vss vss vss 68-system 16-bit bus interface vss vss vdd3 68-system 8bit bus interface vss vdd3 vss 80-system 16bit bus interface vss vdd3 vdd3 80-system 8bit bus interface vdd3 vss id serial peripheral interface (spi) im2-1, im0/id i when a spi mode is selected, the im0 pin is used as the id setting for a device code. cs b i chip s elect pin. low: S6D0110 is selected and can be accessed high: S6D0110 is not selected and cannot be accessed must be fixed at vss level when not in use. rs i register select pin. low: index/status, high: control im2 im1 pin func. pin description vss vss e for a 68-system bus interface, serves as an enable signal to activate data read/write operation. vss vdd3 /wr for an 80-system bus interface, serves as a write strobe signal and writes data at the low level. e ( /wr ,scl) i vdd3 vss scl for a serial peripheral interface, serves as the synchronous clock signal. im2 im1 pin func. pin description vss vss r/w for a 68-system bus interface, serves as a signal to select data read/write operation. low: write , high: read vss vdd3 /rd for an 80-system bus interface, serves as a read strobe signal and reads data at the low level. r / w ( /rd ) i when spi mode is selected, fix this pin at ? vss ? level. db0/sdi i/o bi-directional data input pin for the first bit of 16-bit data bus or serial data of spi. for an 8-bit bus interface , data bus uses db15-db8; fix unused db7-db0 to the vdd 3 or vss level. for a serial peripheral interface ( spi) , the input data is fetched at the rising edge of the scl signal. db1/sdo i/o serves as a 16-bit bi - directional data bus. for an 8-bit bus interface, data transfer uses db15-db8; fix unused db7-db0 to the vdd3 or vss level. for a serial peripheral interface ( spi) , serves as the serial data output pin(sdo). successive bit values are output on the falling edge of the scl signal. db2-db15 i/o serves as a 16-bit bi - directional data bus. for an 8-bit bus interface, data transfer uses db15-db8; fix unused db7-db0 to the vdd 3 or v ss level. resetb1/ resetb2/ resetb3 i reset pin. initializes the lsi when low. must be reset after power-on.
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 18 table 10 . display pin description symbol i/o description s1 - s396 o source driver output pins. the ss bit can change the shift direction of the source signal. for example, if ss = 0, ram address 0000 is output from s1. if ss = 1, it is output from s396. s1, s4, s7, ... s(3n-1) : display r ed (r) (ss = 0) s2, s5, s8, ... s(3n-2) : display g reen (g) (ss = 0) s3, s6, s9, ... s(3n) : display b lue (b) (ss = 0) g1 - g176 o gate driver output pins. the output of driving circuit is whether vgh, output gate selecting level or vgoff, gate non- selecting level. g0, g177 o gate driver output pins for ic maker ? s testing. please, leave it disconnected. cl1 o output pin for one-raster-row-cycle pulse . m o output pin for ac-cycle signa l . flm o output pin for frame-start pulse. eq o output pin for timing for equalizing low : normal display, high : equalizing disptmg o gate off signal in the partial display low : non-display, high : normal output table 11 . oscillator and internal power regulator pin description symbol i/o description osc1/ osc2 i/o connect an external resistor for r-c oscillation. when input the clock from outside, input to osc1, and open osc2. pregb i internal power regulator control input pin. when the internal regulated power (rdvdd) is used as vdd, pregb is fixed to ? low ? level. when the external logic power(vdd3) is used as vdd, pregb is fixed to ? high ? level. rdvdd o internal power regulated-vdd output (typ. 1.9v). when pregb is ? low ? , rdvdd is connected to vdd pin. when pregb is ? high ? , leave this pin open.
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 19 functional description system interface the S6D0110 has five high-speed system interfaces: an 80-system 16-bit/8-bit bus, a 68-system 16-bit/8-bit bus, and a serial interface (spi: serial peripheral interface port). the im2-0 pins select the interface mode. the S6D0110 has three 16-bit registers: an index register (ir), a write data register (wdr), and a read data register (rdr). the ir stores index information for control register and gram. the wdr temporarily stores data to be written into control register and gram . the rdr temporarily stores data read from gram. data written into the gram from the mpu is first written into the wdr and then written into the gram by internal operation automatically. data is read through the rdr when reading from the gram, and the first read data is invalid and the second and the following data are valid . when a logic operation is performed inside of the S6D0110 by using the display data stored in the gram and the data written from the mpu, the data read through the rdr is used. accordingly, the mpu does not need to read data twice nor to fetch the read data into the mpu. this enables high-speed processing. execution time for instruction , ex cept oscillation start , is 0 - clock cycle so that instructions can be written in succession. table 12 . register selection (80-system 8/16 parallel interface) /wr /rd rs operations 0 1 0 write indexes into ir 1 0 0 reads internal status 0 1 1 writes into control registers and gram through wdr 1 0 1 reads from gram through rdr table 13 . register selection (serial peripheral interface) r/w bits rs bits operations 0 0 writes index into ir 1 0 reads internal status 0 1 writes data into control registers and gram through wdr 1 1 reads data from gram through rdr bit operation the S6D0110 supports the following functions: a write data mask function that selects and writes data into the gram in bit units, and a logic operation function that performs logic operations or conditional determination on the display data set in the gram and writes into the gram. with the 16-bit bus interface, these functions can greatly reduce the processing loads of the mpu graphics software and can rewrite the display data in the gram at high speed. for details, see the graphics operation function section.
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 20 address counter (ac) the address counter (ac) assign addresses to the gram. when an address set instruction is written into the ir, the address information is sent from the ir to the ac. after writing into the gram, the ac is automatically increased /decreased by 1 according to id1-0 bit of control register. after reading data from gram , the ac is not updated. a window address function allows data to be written only to a window area specified by gram. graphics ram (gram) the graphics ram (gram) has sixteen bits/pixel and stores the bit-pattern data for 132 rgb x 176 dot display. grayscale voltage generator the grayscale voltage circuit generates a lcd driver circuit that corresponds to the grayscale levels as specified in the grayscale ? -adjusting resistor. 65 , 536 colors can be displayed at the same time. for details, see the ? -adjusting resistor section . timing generator the timing generator generates timing signals for the operation of internal circuits such as gram. the ram read timing for display and the internal operation timing for mpu access is generated separately to avoid interference with one another. the timing generator generates the interface signals (m, flm, cl1, eq, disptmg) . oscillation circuit (osc) the S6D0110 can provide r-c oscillation simply through the addition of an external oscillation-resistor between the osc1 and osc2 pins. the appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. clock pulses can also be supplied externally. since r-c oscillation stops during the standby mode, current consumption can be reduced. for details, see the oscillation circuit section. source driver circuit th is liquid crystal display source driver circuit consists of 396 source drivers (s1 to s396). display pattern data is latched when 396-bit data has arrived. the latched data then enables the source drivers to generate drive waveform outputs. the ss bit can change the shift direction of 396-bit data by selecting an appropriate direction for the device-mounted configuration. gate driver circuit th is liquid crystal display gate driver circuit consists of 178 gate drivers ( g0 to g177 ). the vgh or vgoff level is output by the signal from the gate control circuit. g0 and g177 are ic maker ? s test pins.
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 21 power supply circuit figure 2 shows a configuration of the voltage generation circuit for S6D0110 . the step-up circuits consist of step- up circuits 1 to 4. step-up circuit 1 doubles or triples the voltage supplied to vci1, and that voltage is doubled, tripled, or quadrupled in step-up circuit 2. step-up circuit 3 reverses the vgh level with reference to vss or vbs and generates the vgl level. step-up circuit 4 reverses the vci level with reference to vss and generates the vcl level. these step-up circuits generate power supplies avdd, gvdd, vgh, vgl, vgoff, and vcom. reference voltages gvdd, vcom, and vgoff for the grayscale voltage are amplified in amplification circuits 1 and 2 from the internal- voltage adjustment circuit or the regp or regn voltage, and generate each level depending on that voltage. connect vcom to the tft panel. amplfiication circuit2 (vgoff adjustment) amplification circuit1 (vdh adjustment) vcomh adjustment circuit vcom amplitude adjustment circuit vdhout voltage adjustment circuit regulator vciout vci vci vcomr vdh output amplifier vdh step-up circuit 1 step-up circuit 2 step-up circuit 3 vreg2 out vreg1 out vreg2 vreg1 regp regn adjust vcomh voltage (when using an external variable resistor) vci when using vciout vci1 c11- c11+ c12- c12+ vlout1 ddvdh vci2 c21- c21+ c22- c22+ c23- c23+ vlout2 vgh vci3 c31- c31+ vlout3 vgl vci4 c41- c41+ vlout4 vcl vgl vgh ddvdh vcomh output amplifier vcoml output amplifier vcomh vcom vcoml vgoffh output amplifier vgoffl output amplifier vgoffh vgoffout vgoffl vgoffh amplitude adjustment circuit vss vss vdd vci step-up circuit 4 figure 5 . configuration of the internal power-supply circuit notes: use the 1uf capacitor.
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 22 pattern diagrams for voltage setting the following f igure shows a pattern diagram for the voltage setting and an example of waveforms . vgh(+7 ~ +20v) avdd(+3.5 ~ +5.5v) ddvdh vreg1out gvdd(+3.0 ~ +5.0v) vdh vcomh(+3.0 ~ vdh) vcom4-0 vdv4-0 bt2-0 vrh3-0 vci1 (-1 times) bt2-0 vrl3-0 (-1 times) vcoml(vcl+0.5 to 1.0v) vcl vgoffh(to -5.0v) vgoffl (vgl+0.5 to -16.0v) vgl(-9 to -16.5v) vreg2out vci(2.5v ~ 3.3v) vdd(1.8v ~ 3.3v) vss(0v) vc2-0 note: adjust the conditions of avdd-gvdd>0.5v, vcoml-vcl>0.5v, and vgoff-vgl>0.5v with loads because they differ depending on the display load to be driven. in addition, vci can be directly input to vci1. vgh gvdd(vdh) vcomh vcoml vgoffh vgoffl vcom sn(source output) gn(gate output) figure 6 . pattern diagram and an example of waveforms
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 23 set up flow of power supply apply the power in a sequence as shown in figure 7 . the stable time of the oscillation circuit, step-up circuit, and operational amplifier depend on the external resistor or capacitance. 10ms or more (stable time of the oscillation circuit) power supply (vdd on) power-on reset and display off 1ms issues instructions for power supply setting (1) bits for display off. dte=0 d1-0=00 gon=0 pon=0 normal display bits for display on: dte =1, d1- 0=11, gon=1 bits for power-supply initial setting: vcom, vc2- 0, vrh3- 0, cad, vrl3- 0, vcm4-0, vdv4- 0, vrn4-0, vrp4-0 (setting of the source- driver grayscale voltage) issues instruction for power supply setting (2) bits for power-supply operation start setting: bt2-0, dc2- 0, ap2-0 bits for source-driver operational amplifier operaton-start setting: sap2-0 bits for step-up circuit3 operation start pon=1 issues instruction for power supply setting (3) display off bits for display off: dte =0, d1- 0=00, gon=0 instruction for power supply setting(1) bits for source-driver operational amplifier operation-stop setting: sap2-0 instruction for power supply setting(2) bits for power supply stop setting: ap2-0 for operational amplifier, dc2-0 for step-up circuit display off sequence* power supply (vdd off) issues instruction for other mode setting display-on sequence* diplay on bits for display on: dte =1, d1- 0=11, gon=1 50ms or more (stable times of step-up circuit 1 and 2) 200ms or more (stable time of the step- up operational amplifier) power-on sequence power-off sequence figure 7 . set up flow of power supply
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 24 gram address table 14 . gram address (ss= ? 0 ? ) s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 ??? s385 s386 s387 s388 s389 s390 s391 s392 s393 s394 s395 s396 db db db db db db db db db db db db db db db db 15 0 15 0 15 0 15 0 15 0 15 0 15 0 15 0 g1 g176 ??? g2 g175 ??? g3 g174 ??? g4 g173 ??? g5 g172 ??? g6 g171 ??? g7 g170 ??? g8 g169 ??? g9 g168 ??? g10 g167 ??? g11 g166 ??? g12 g165 ??? g13 g164 ??? g14 g163 ??? g15 g162 ??? g16 g161 ??? g17 g160 ??? g18 g159 ??? g19 g158 ??? g20 g157 ??? g169 g168 ??? g170 g167 ??? g171 g166 ??? g172 g165 ??? g173 g164 ??? g174 g163 ??? g175 g162 ??? g176 g161 ??? "af80"h "af81"h "af80"h "af83"h "ae80"h "ae81"h "ae80"h "ae83"h "ad80"h "ad81"h "ad80"h "ad83"h "ac80"h "ac81"h "ac80"h "ac83"h "ab80"h "ab81"h "ab80"h "ab83"h "aa80"h "aa81"h "aa80"h "aa83"h "a980"h "a981"h "a980"h "a983"h "a880"h "a881"h "a880"h "a883"h ?? ?? ?? ?? "1380"h "1381"h "1382"h "1383"h "1280"h "1281"h "1282"h "1283"h "1180"h "1181"h "1182"h "1183"h "1080"h "1081"h "1082"h "1083"h "0f80"h "0f81"h "0f82"h "0f83"h "0e80"h "0e81"h "0e82"h "0e83"h "0d80"h "0d81"h "0d82"h "0d83"h "0c80"h "0c81"h "0c82"h "0c83"h "0b80"h "0b81"h "0b82"h "0b83"h "0a80"h "0a81"h "0a82"h "0a83"h "0980"h "0981"h "0982"h "0983"h "0880"h "0881h "0882"h "0883"h "0780"h "0781"h "0782"h "0783"h "0680"h "0681"h "0682"h "0683"h "0580"h "0581"h "0582"h "0583"h "0480"h "0481"h "0482"h "0483"h "0380"h "0381"h "0382"h "0383"h "0280"h "0281"h "0282"h "0283"h "0180"h "0181"h "0182"h "0183"h "0080"h "0081"h "0082"h "0083"h ?? ?? ?? ?? "af00"h "af01"h "af02"h "af03"h "ae00"h "ae01"h "ae02"h "ae03"h "ad00"h "ad01"h "ad02"h "ad03"h "ac00"h "ac01"h "ac02"h "ac03"h "ab00"h "ab01"h "ab02"h "ab03"h "aa00"h "aa01"h "aa02"h "aa03"h "a900"h "a901"h "a902"h "a903"h "a800"h "a801"h "a802"h "a803"h ?? ?? ?? ?? ?? ?? "1300"h "1301"h "1302"h "1303"h "1200"h "1201"h "1202"h "1203"h "1100"h "1101"h "1102"h "1103"h "1000"h "1001"h "1002"h "1003"h "0f00"h "0f01"h "0f02"h "0f03"h "0e00"h "0e01"h "0e02"h "0e03"h "0d00"h "0d01"h "0d02"h "0d03"h "0c00"h "0c01"h "0c02"h "0c03"h "0b00"h "0b01"h "0b02"h "0b03"h "0a00"h "0a01"h "0a02"h "0a03"h "0900"h "0901"h "0902"h "0903"h "0800"h "0801"h "0802"h "0803"h "0700"h "0701"h "0702"h "0703"h "0600"h "0601"h "0602"h "0603"h "0500"h "0501"h "0502"h "0503"h "0400"h "0401"h "0402"h "0403"h "0300"h "0301"h "0302"h "0303"h "0200"h "0201"h "0202"h "0203"h "0100"h "0101"h "0102"h "0103"h ?? ?? ?? "0000"h "0001"h "0002"h "0003"h s/g output gs=0 gs=1 ??
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 25 table 15 . gram address (ss= ? 1 ? ) s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 ??? s385 s386 s387 s388 s389 s390 s391 s392 s393 s394 s395 s396 db db db db db db db db db db db db db db db db 15 0 15 0 15 0 15 0 15 0 15 0 15 0 15 0 g1 g176 ??? g2 g175 ??? g3 g174 ??? g4 g173 ??? g5 g172 ??? g6 g171 ??? g7 g170 ??? g8 g169 ??? g9 g168 ??? g10 g167 ??? g11 g166 ??? g12 g165 ??? g13 g164 ??? g14 g163 ??? g15 g162 ??? g16 g161 ??? g17 g160 ??? g18 g159 ??? g19 g158 ??? g20 g157 ??? g169 g168 ??? g170 g167 ??? g171 g166 ??? g172 g165 ??? g173 g164 ??? g174 g163 ??? g175 g162 ??? g176 g161 ??? s/g output gs=0 gs=1 ?? ?? ?? ?? ?? ?? ?? ?? "0083"h "0082"h "0081"h "0080"h "0003"h "0002"h "0001"h "0000"h "0183"h "0182"h "0181"h "0180"h "0103"h "0102"h "0101"h "0100"h "0283"h "0282"h "0281"h "0280"h "0203"h "0202"h "0201"h "0200"h "0383"h "0382"h "0381"h "0380"h "0303"h "0302"h "0301"h "0300"h "0483"h "0482"h "0481"h "0480"h "0403"h "0402"h "0401"h "0400"h "0583"h "0582"h "0581"h "0580"h "0503"h "0502"h "0501"h "0500"h "0683"h "0682"h "0681"h "0680"h "0603"h "0602"h "0601"h "0600"h "0783"h "0782"h "0781"h "0780"h "0703"h "0702"h "0701"h "0700"h "0883"h "0882"h "0881h "0880"h "0803"h "0802"h "0801"h "0800"h "0983"h "0982"h "0981"h "0980"h "0903"h "0902"h "0901"h "0900"h "0a83"h "0a82"h "0a81"h "0a80"h "0a03"h "0a02"h "0a01"h "0a00"h "0b83"h "0b82"h "0b81"h "0b80"h "0b03"h "0b02"h "0b01"h "0b00"h "0c83"h "0c82"h "0c81"h "0c80"h "0c03"h "0c02"h "0c01"h "0c00"h "0d83"h "0d82"h "0d81"h "0d80"h "0d03"h "0d02"h "0d01"h "0d00"h "0e83"h "0e82"h "0e81"h "0e80"h "0e03"h "0e02"h "0e01"h "0e00"h "0f83"h "0f82"h "0f81"h "0f80"h "0f03"h "0f02"h "0f01"h "0f00"h "1083"h "1082"h "1081"h "1080"h "1003"h "1002"h "1001"h "1000"h "1183"h "1182"h "1181"h "1180"h "1103"h "1102"h "1101"h "1100"h "1283"h "1282"h "1281"h "1280"h "1203"h "1202"h "1201"h "1200"h "1302"h "1301"h "1300"h "1383"h "1382"h "1381"h "1380"h ?? ?? ?? "1303"h ?? ?? ?? ?? ?? ?? "a880"h "a881"h "a880"h "a803"h "a802"h "a801"h ?? "a800"h "a983"h "a980"h "a981"h "a980"h "a903"h "a902"h "a901"h "a900"h "a883"h "aa83"h "aa80"h "aa81"h "aa80"h "aa03"h "aa02"h "aa01"h "aa00"h "ab83"h "ab80"h "ab81"h "ab80"h "ab03"h "ab02"h "ab01"h "ab00"h "ac83"h "ac80"h "ac81"h "ac80"h "ac03"h "ac02"h "ac01"h "ac00"h "ad83"h "ad80"h "ad81"h "ad80"h "ad03"h "ad02"h "ad01"h "ad00"h "ae83"h "ae80"h "ae81"h "ae80"h "ae03"h "ae02"h "ae01"h "ae00"h "af83"h "af80"h "af81"h "af80"h "af03"h "af02"h "af01"h "af00"h
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 26 instructions the S6D0110 uses the 16-bit bus architecture. before the internal operation of the S6D0110 starts, control information is temporarily stored in the registers described below to allow high-speed interfacing with a high- performance microcomputer. the internal operation of the S6D0110 is determined by signals sent from the microcomputer. these signals, which include the register selection signal (rs), the read/write signal (r/w), and the data bus signals (db15 to db0), make up the S6D0110 instructions. there are nine categories of instructions that: - specify the index - read the status - control the display - control power management - process the graphics data - set internal gram addresses - transfer data to and from the internal gram - set grayscale level for the internal grayscale palette table - interface with the gate driver and power supply ic normally, instructions that write data are used the most. however, an auto-update of internal gram addresses after each data write can lighten the microcomputer program load. as instructions are executed in 0 cycles, they can be written in succession.
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 27 instruction table table 16 . instruction table 1 reg. no r/w rs db 15 db 1 4 db 1 3 db 1 2 db 1 1 db 1 0 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 register n ame / description ir 0 0 * * * * * * * * * id6 id5 id4 id3 id2 id1 id0 index / sets the index register value sr 1 0 l7 l6 l5 l4 l3 l2 l1 l0 0 0 0 0 0 0 0 0 status read / reads the driving raster-row position 0 1 * * * * * * * * * * * * * * * 1 start oscillation / starts the oscillation circuit r00h 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 device code read / read 0110h r01h 0 1 0 0 0 0 0 sm gs ss 0 0 0 nl4 nl3 nl2 nl1 nl0 driver output control / sm: gate driver division drive control gs: gate driver shift direction ss: source driver shift direction nl4-0: number of driving lines r02h 0 1 0 0 0 0 fld1 fdl0 b/c eor 0 0 nw5 nw4 nw3 nw2 nw1 nw0 lcd-driving-waveform control / fld1-0: number of interlaced field b/c: lcd drive ac waveform nw5-0: number of n-raster-row of c- pattern r03h 0 1 0 0 sap2 sap1 sap0 bt2 bt1 bt0 dc2 dc1 dc0 ap2 ap1 ap0 slp stb power control 1 / sap2-0: bt2-0: dc2-0: ap2-0: slp: stb: r04h 0 1 cad 0 0 vrn4 vrn3 vrn2 vrn1 vrn0 0 0 0 vrp4 vrp3 vrp2 vrp1 vrp0 power control 2 / cad: vrn4-0: vrp4-0: r05h 0 1 0 0 0 bgr 0 0 hwm 0 0 0 i/d1 i/d0 am lg2 lg1 lg0 entry mode / bgr: hwm: i/d1-0: am: lg2-0: r06h 0 1 cp15 cp14 cp13 cp12 cp11 cp10 cp9 cp8 cp7 cp6 cp5 cp4 cp3 cp2 cp1 cp0 compare register / r07h 0 1 0 0 0 pt1 pt0 vle2 vle1 spt 0 0 gon dte cl rev d1 d0 display control / pt1-0: vle2-1: spt: gon: dte: cl: rev: d1-0: r08h 0 1 0 0 0 0 fp3 fp2 fp1 fp0 0 0 0 0 bp3 bp2 bp1 bp0 blank period control 1/ bp3-0: back porch setting fp3-0: front porch setting r09h 0 1 0 0 0 0 blp1 3 blp1 2 blp1 1 blp1 0 blp2 3 blp2 2 blp2 1 blp2 0 0 0 0 0 blank period control 2/ r0bh 0 1 no1 no0 sdt1 sdt0 eq1 eq0 div1 div0 0 0 0 0 rtn3 rtn2 rtn1 rtn0 frame cycle control / no1-0: sdt1-0: eq1-0: dvi1-0: rtn3-0: r0ch 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 vc2 vc1 vc0 power control 3 / vc2-0: r0dh 0 1 0 0 0 0 vrl3 vrl2 vrl1 vrl0 0 0 0 pon vrh3 vrh2 vrh1 vrh0 power control 4 / vrl3-0: pon: vrh3-0: r0eh 0 1 0 0 vco mg vdv4 vdv3 vdv2 vdv1 vdv0 0 0 0 vcm4 vcm3 vcm2 vcm1 vcm0 power control 5 / vcomg: vdv4-0: vcm4-0: r0fh 0 1 0 0 0 0 0 0 0 0 0 0 0 scn4 scn3 scn2 scn1 scn0 gate scan position / scn4-0: scan starting position of gate
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 28 table 17 . instruction table 2 reg. no r/w rs db 15 db 1 4 db 1 3 db 1 2 db 1 1 db 1 0 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 register n ame / description r11h 0 1 0 0 0 0 0 0 0 0 vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 vertical scroll control / vl7-0: r14h 0 1 se17 se16 se15 se14 se13 se12 se11 se10 ss17 ss16 ss15 ss14 ss13 ss12 ss11 ss10 1 st screen driving position / se17-10: ss17-10 r15h 0 1 se27 se26 se25 se24 se23 se22 se21 se20 ss27 ss26 ss25 ss24 ss23 ss22 ss21 ss20 2 nd screen driving position / se27-20: ss27-20 r16h 0 1 hea7 hea6 hea5 hea4 hea3 hea2 hea1 hea0 hsa7 hsa6 hsa5 hsa4 hsa3 hsa2 hsa1 hsa0 horizontal ram address position / hea7-0: hsa7-0 r17h 0 1 vea7 vea6 vea5 vea4 vea3 vea2 vea1 vea0 vsa7 vsa6 vsa5 vsa4 vsa3 vsa2 vsa1 vsa0 vertical ram address position / hea7-0: hsa7-0 r20h 0 1 wm15 wm14 wm13 wm12 wm11 wm10 wm9 wm8 wm7 wm6 wm5 wm4 wm3 wm2 wm1 wm0 ram write data mask / wm15-0: r21h 0 1 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ram address set / ad15-0: 0 1 wd15 wd14 wd13 wd12 wd11 wd10 wd9 wd8 wd7 wd6 wd5 wd4 wd3 wd2 wd1 wd0 write data to gram / wd15-0: r22h 1 1 rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 read data from gram / rd15-0: r30h 0 1 0 0 0 0 0 pkp 12 pkp 11 pkp 10 0 0 0 0 0 pkp 02 pkp 01 pkp 00 gamma control 1 / adjust gamma voltage r31h 0 1 0 0 0 0 0 pkp 32 pkp 31 pkp 30 0 0 0 0 0 pkp 22 pkp 21 pkp 20 gamma control 2 / adjust gamma voltage r32h 0 1 0 0 0 0 0 pkp 52 pkp 51 pkp 50 0 0 0 0 0 pkp 42 pkp 41 pkp 40 gamma control 3 / adjust gamma voltage r33h 0 1 0 0 0 0 0 prp 12 prp 11 prp 10 0 0 0 0 0 prp 02 prp 01 prp 00 gamma control 4 / adjust gamma voltage r34h 0 1 0 0 0 0 0 pkn 12 pkn 11 pkn 10 0 0 0 0 0 pkn 02 pkn 01 pkn 00 gamma control 5 / adjust gamma voltage r35h 0 1 0 0 0 0 0 pkn 32 pkn 31 pkn 30 0 0 0 0 0 pkn 22 pkn 21 pkn 20 gamma control 6 / adjust gamma voltage r36h 0 1 0 0 0 0 0 pkn 52 pkn 51 pkn 50 0 0 0 0 0 pkn 42 pkn 41 pkn 40 gamma control 7 / adjust gamma voltage r37h 0 1 0 0 0 0 0 prn 12 prn 11 prn 10 0 0 0 0 0 prn 02 prn 01 prn 00 gamma control 8 / adjust gamma voltage
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 29 instruction descriptions index the index instruction specifies the ram control indexes (r00h to r3fh). it sets the register number in the range of 00000 to 111111 in binary form. however, r40 to r44 are disabled since they are test registers. r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 0 * * * * * * * * * id6 id5 id4 id3 id2 id1 id0 status read the status read instruction read out the internal status of the ic . r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 r 0 l7 l6 l5 l4 l3 l2 l1 l0 0 0 0 0 0 0 0 0 l7 ? 0 : indicate the driving raster-row position where the liquid crystal display is being driven. start oscillation (r00h) the start oscillation instruction restarts the oscillator from the halt state in the standby mode. after this instruction, wait at least 10 ms for oscillation to stabilize before giving the next instruction. (see the standby mode section) if this register is read forcibly, *0110h is read. r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 * * * * * * * * * * * * * * * 1 r 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 30 driver output control (r01h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 0 0 0 0 0 sm gs ss 0 0 0 nl4 nl3 nl2 nl1 nl0 gs : selects the output shift direction of the gate driver. when gs = 0, g1 shifts to g 176 . when gs = 1, g176 shifts to g1. sm : select the division drive method of the gate driver. when sm = 0, even/odd division is selected; sm = 1, upper/lower division drive is selected. various connections between tft panel and the ic can be supported with the combination of sm and gs bit. ss : selects the output shift direction of the source driver. when ss = 0, s1 shifts to s396. when ss = 1, s396 shifts to s1. when ss = 0, color is assigned from s1. when ss = 1, color is assigned from s396. re-write to the ram when intending to change the ss bit. nl4 ? 0 : specify number of lines for the lcd drive. number of lines for the lcd drive can be adjusted for every eight raster-rows. gram address mapping does not depend on the setting value of the drive duty ratio. select the set value for the panel size or higher. table 18 . nl bit and drive duty (scn4-0=00000) nl4 nl3 nl2 nl1 nl0 display size number of lcd driver lines gate driver used 0 0 0 0 0 setting disabled setting disabled setting disabled 0 0 0 0 1 396 x 16 dots 16 g1 to g16 0 0 0 1 0 396 x 24 dots 24 g1 to g24 0 0 0 1 1 396 x 32 dots 32 g1 to g32 0 0 1 0 0 396 x 40 dots 40 g1 to g40 0 0 1 0 1 396 x 48 dots 48 g1 to g48 0 0 1 1 0 396 x 56 dots 56 g1 to g56 0 0 1 1 1 396 x 64 dots 64 g1 to g64 0 1 0 0 0 396 x 72 dots 72 g1 to g72 0 1 0 0 1 396 x 80 dots 80 g1 to g80 0 1 0 1 0 396 x 88 dots 88 g1 to g88 0 1 0 1 1 396 x 96 dots 96 g1 to g96 0 1 1 0 0 396 x 104 dots 104 g1 to g104 0 1 1 0 1 396 x 112 dots 112 g1 to g112 0 1 1 1 0 396 x 120 dots 120 g1 to g120 0 1 1 1 1 396 x 128 dots 128 g1 to g128 1 0 0 0 0 396 x 136 dots 136 g1 to g136 1 0 0 0 1 396 x 144 dots 144 g1 to g144 1 0 0 1 0 396 x 152 dots 152 g1 to g152 1 0 0 1 1 396 x 160 dots 160 g1 to g160 1 0 1 0 0 396 x 168 dots 168 g1 to g168 1 0 1 0 1 396 x 176 dots 176 g1 to g176 n ote : blank period ( a ll gates output vgoff level) have to be inserted after all gates are scanned.
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 31 lcd-driving-waveform control (r02h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 0 0 0 0 fld 1 fld 0 b/c eor 0 0 nw5 nw4 nw3 nw2 nw1 nw0 fld1-0 : these bits are for the set up of the interlaced driver ? s n raster-row. see the following table and figure for the set up value and field raster-row and scanning method. table 19 . association chart for scanning fld1-0 and n raster-row fld1 fld0 scanning method 0 0 set up disabled 0 1 1 field 1 0 set up disabled 1 1 3 field (interlaced) g1 4 g2 4 g3 4 ..... g174 4 g175 4 g176 tft panel (a) when fld1-0= 01(normal scanning) g1 4 g4 4 g7 4 ..... 4 g174 tft panel g2 4 g5 4 g8 4 ..... 4 g175 g3 4 g6 4 g9 4 ..... 4 g176 tft panel tft panel 1 frame frame 1/3 frame 2/3 frame 3/3 (b) when fld1-0= 11(interlaced scanning) figure 8 . n raster-row interlaced scanning method b/c : when b/c = 0, a b-pattern waveform is generated and alternates in every frame for lcd drive. when b/c = 1, a n raster-row waveform is generated and alternates in each raster-row specified by bits eor and nw4 ? nw0 in the lcd-driving-waveform control register (r02h) . for details, see the n-raster-row reversed ac drive section.
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 32 eor: when the c-pattern waveform is set (b/c = 1) and eor = 1, the odd/even frame-select signals and the n- raster-row reversed signals are eored (exclusive-or) for alternating drive. eor is used when the lcd is not alternated by combining the set values of the number of the lcd drive raster-row and the n raster-row. for details, see the n-raster-row reversed ac drive section. nw5 ? 0: specify the number of raster-rows that will alternate in the c-pattern waveform setting (b/c = 1). nw4 ? nw0 alternate for every set value + 1 raster-row, and the first to the 64th raster-rows can be selected.
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 33 power control 1 (r03h) power control 2 (r04h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 0 0 sap 2 sap 1 sap 0 bt2 bt1 bt0 dc2 dc1 dc0 ap2 ap1 ap0 slp stb w 1 cad 0 0 vrn 4 vrn 3 vrn 2 vrn 1 vrn 0 0 0 0 vrp 4 vrp 3 vrp 2 vrp 1 vrp 0 sap2-0: the amount of fixed current from the fixed current source in the operational amplifier for the source driver is adjusted. when the amount of fixed current is large, lcd driving ability and the display quality become high, but the current consumption is increased. adjust the fixed current considering the display quality and the current consumption. during no display, when sap2-0 = ? 000 ? , the current consumption can be reduced by ending the operational amplifier and step-up circuit operation. sap2 sap1 sap0 amount of current in operational amplifier 0 0 0 operation of the operational amplifier and step-up circuit stops. 0 0 1 small 0 1 0 small or medium 0 1 1 medium 1 0 0 medium or large 1 0 1 large 1 1 0 setting inhibited 1 1 1 setting inhibited bt2 ? 0: the output factor of step-up is switched. adjust scale factor of the step-up circuit by the voltage used. when the step-up operating frequency is high, the driving ability of the step-up circuit and the display quality become high, but the current consumption is increased. adjust the frequency considering the display quality and the current consumption. bt2 bt1 bt0 vlout1 output vlout2 output notes* 0 0 0 2 x vci1 3 x vci2 vlout2 = vci1 x six times 0 0 1 2 x vci1 4 x vci2 vlout2 = vci1 x eight times 0 1 0 3 x vci1 3 x vci2 vlout2 = vci1 x nine times 0 1 1 3 x vci1 2 x vci2 vlout2 = vci1 x six times 1 0 0 2 x vci1 vci1 + 2 x vci2 vlout2 = vci1 x five times 1 0 1 2 x vci1 vci1 + 3 x vci2 vlout2 = vci1 x seven times 1 1 0 step-up stopped 3 x vci2 vlout2 = vci2 x three times 1 1 1 step-up stopped 4 x vci2 vlout2 = vci2 x four times notes: the step-up factors of vlout2 are derived from vci1 when vlout1 and vci2 are shorted. the conditions of vlout1 5.5v and vlout2 15.0v must be satisfied.
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 34 dc2-0: the operating frequency in the step-up circuit is selected. when the step-up operating frequency is high, the driving ability of the step-up circuit and the display quality become high, but the current consumption is increased. adjust the frequency considering the display quality and the current consumption. dc2 dc1 dc0 step-up cycle in step-up circuit1 step-up cycle in step-up circuit 2/3/4 0 0 0 dcclk / 1 dcclk / 4 0 0 1 dcclk / 2 dcclk / 4 0 1 0 dcclk / 4 dcclk / 4 0 1 1 dcclk / 2 dcclk / 16 1 0 0 dcclk dcclk / 8 1 0 1 dcclk / 2 dcclk / 8 1 1 0 dcclk / 4 dcclk / 8 1 1 1 dcclk / 4 dcclk / 16 ap2 ? 0: the amount of fixed current in the operational amplifier for the power supply can be adjusted. when the amount of fixed current is large, the lcd driving ability and the display quality become high, but the current consumption is increased. adjust the fixed current considering the display quality and the current consumption. during no display, when ap2-0 = ? 000 ? , the current consumption can be reduced by ending the operational amplifier and step-up circuit operation. ap2 ap1 ap0 amount of current in operational amplifier 0 0 0 operation of the operational amplifier and step-up circuit stops. 0 0 1 small 0 1 0 small or medium 0 1 1 medium 1 0 0 medium or large 1 0 1 large 1 1 0 setting inhibited 1 1 1 setting inhibited slp: when slp = 1, the S6D0110 enters the sleep mode, where the internal display operations are halted except for the r-c oscillator, thus reducing current consumption. only the following instructions can be executed during the sleep mode. - power control (bt2 ? 0, dc3 ? 0, ap2 ? 0, slp, stb, vc2-0, cad, vr3-0, vrl3-0, vrh4-0, vcomg, vdv4- 0, and vcm4-0 bits) during the sleep mode, the other gram data and instructions cannot be updated although they are retained and g1 to g228 output is fixed to vss level, and register set-up is protected (maintained).
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 35 stb: when stb = 1, the S6D0110 enters the standby mode, where display operation completely stops, halting all the internal operations including the internal r-c oscillator. further, no external clock pulses are supplied. for details, see the standby mode section. only the following instructions can be executed during the standby mode. - standby mode cancel(stb = ? 0 ? ) - start oscillation cad: set this bit according to the structure for the tft-display retention volume. cad = 0: set this bit when the cst retention volume is structured. in this case, vgoff level is fixed to vgoffl level regardless of the vcom alternating drive. cad = 1: set this bit when the cadd retention volume is structured. at the vcom alternating drive, the vgoff voltage is output in the vgoffl voltage reference by the amount of vcom alternating amplitude. vrp4-0: control oscillation (positive polarity) of 64-grayscale. for details, see the oscillation adjusting circuit section. vrn4-0: control oscillation (negative polarity) of 64-grayscale. for details, see the oscillation adjusting circuit section.
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 36 power control 3 (r0ch) power control 4 (r0dh) power control 5 (r0eh) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 0 0 0 0 0 0 0 0 0 0 0 0 0 vc2 vc1 vc0 w 1 0 0 0 0 vrl 3 vrl 2 vrl 1 vrl 0 0 0 0 pon vrh 3 vrh 2 vrh 1 vrh 0 w 1 0 0 vco mg vdv 4 vdv 3 vdv 2 vdv 1 vdv 0 0 0 0 vcm 4 vcm 3 vcm 2 vcm 1 vcm 0 vc2-0: adjust reference voltage of vreg1, vreg2out and vci out to optional rate of v ci . also, when vc2 = ? 1 ? , it is possible to stop the internal reference voltage generator. this leads to optional power on for vreg1out/vci out with regp and vreg2out with regn externally. vc2 vc1 vc0 internal reference voltage (regp) of vreg1out and vciout internal reference voltage (regn) of vreg2out 0 0 0 0.92 x vci 0.08 x vci 0 0 1 0.83 x vci 0.17 x vci 0 1 0 0.73 x vci 0.27 x vci 0 1 1 0.68 x vci 0.32 x vci 1 0 0 vci vss 1 * * stops generation of the internal reference voltages of vreg1out and vciout (regp can be input externally) stops generation of the internal reference voltage of vreg2out (regn can be input externally). notes: leave these settings open because the voltage other than that for halting the internal circuit is output for regp and regn. v rl3- 0: set magnification of amplification for vreg2out voltage (voltage for the reference voltage, vreg2 while generating vgoffout.) it allows magnifying the amplification of regn from 2 to 8.5 times. vrl 3 vrl 2 vrl 1 vrl 0 vreg2out voltage vrl 3 vrl 2 vrl 1 vrl 0 vreg2out voltage 0 0 0 0 -(vci ? regn) x 3.0 1 0 0 0 -(vci ? regn) x 6.5 0 0 0 1 -(vci ? regn) x 3.5 1 0 0 1 -(vci ? regn) x 7.0 0 0 1 0 -(vci ? regn) x 4.0 1 0 1 0 -(vci ? regn) x 7.5 0 0 1 1 -(vci ? regn) x 4.5 1 0 1 1 -(vci ? regn) x 8.0 0 1 0 0 -(vci ? regn) x 5.0 1 1 0 0 -(vci ? regn) x 8.5 0 1 0 1 -(vci ? regn) x 5.5 1 1 0 1 -(vci ? regn) x 9.0 0 1 1 0 -(vci ? regn) x 6.0 1 1 1 0 -(vci ? regn) x 9.5 0 1 1 1 stopped 1 1 1 1 stopped notes: 1. these settings apply when the internal reference-voltage generation circuit is stopped and the vreg2out voltage is generated specifying regn as the reference voltage. 2. adjust the settings between the voltage set by (vci ? vc2-0) or the (vci ? regn) voltage and vrl0 to vrl3 so that the vreg2out voltage is higher than ? 16.0 v. 3. the vreg2out voltage is the factor when vci is the reference voltage.
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 37 pon: this is an operation-starting bit for the booster circuit 4. pon = 0 is to stop and pon = 1 to start operation. for further information about timing for adjusting to the pon = 1, please refer to the set up flow of p ower supply circuit . vrh 3 -0: set the amplified factor of the vreg1out voltage (the voltage for the reference voltage , vreg2 while generating vgoffout) . it allows to amplify from 1.45 to 2.85 times of regn input voltage. vrh 3 vrh 2 vrh 1 vrh 0 vreg1out voltage vrh 3 vrh 2 vrh 1 vrh 0 vreg1out voltage 0 0 0 0 regp x 1.45 times 1 0 0 0 regp x 2.175 times 0 0 0 1 regp x 1.55 times 1 0 0 1 regp x 2.325 times 0 0 1 0 regp x 1.65 times 1 0 1 0 regp x 2.475 times 0 0 1 1 regp x 1.75 times 1 0 1 1 regp x 2.625 times 0 1 0 0 regp x 1.80 times 1 1 0 0 regp x 2.700 times 0 1 0 1 regp x 1.85 times 1 1 0 1 regp x 2.775 times 0 1 1 0 regp x 1.90 times 1 1 1 0 regp x 2.850 times 0 1 1 1 stopped 1 1 1 1 stopped notes: 1. these settings apply when the internal reference-voltage generation circuit is stopped and the vreg1out voltage is generated specifying regp as the reference voltage. 2. adjust the settings between the voltage set by vc2-0 or the regp voltage and vrh0 to vrh3 so that the vreg1out voltage is lower than 5.0 v. vcomg: when vcomg = 1, vcoml voltage can output to negative voltage (-5v). when vcomg = 0, vcoml voltage becomes vss and stops the amplifier of the negative voltage. therefore, low power consumption is accomplished. also, when vcomg = 0 and when vcom is driven in a/c, set up of the vdv4-0 is invalid. in this case, adjustment of vcom/vgoff a/c oscillation must be adjusted vcomh with vcm4-0. vdv4-0: set the alternating amplitudes of vcom and vgoff at the vcom alternating drive. these bits amplify vcom and vgoff 0.6 to 1.23 times the vreg1 voltage. when the vcom alternation is not driven, the settings become invalid. vdv 4 vdv 3 vdv 2 vdv 1 vdv 0 vcom amplitude vdv 4 vdv 3 vdv 2 vdv 1 vdv 0 vcom amplitude 0 0 0 0 0 vreg1 x 0.60 1 0 0 0 1 vreg1 x 1.08 0 0 0 0 1 vreg1 x 0.63 1 0 0 1 0 vreg1 x 1.11 0 0 0 1 0 vreg1 x 0.66 1 0 0 1 1 vreg1 x 1.14 : : : : : : 1 0 1 0 0 vreg1 x 1.17 0 1 1 0 0 vreg1 x 0.96 1 0 1 0 1 vreg1 x 1.20 0 1 1 0 1 vreg1 x 0.99 1 0 1 1 0 vreg1 x 1.23 0 1 1 1 0 vreg1 x 1.02 1 0 1 1 1 setting inhibited 0 1 1 1 1 setting inhibited 1 1 * * * setting inhibited 1 0 0 0 0 vreg1 x 1.05 notes : adjust the settings between vreg1 and vdv0 to vdv4 so that the vcom and vgoff amplitudes are lower than 6.0 v.
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 38 vcm4-0: set the vcomh voltage (a high-level voltage at the vcom alternating drive). these bits amplify the vcomh voltage 0.4 to 0.98 times the vreg1 voltage. when vcom4-0 = 1, the adjustment of the internal volume stops, and vcomh can be adjusted from vcomr by an external resistor. vcm4 vcm3 vcm2 vcm1 vcm0 vcomh voltage 0 0 0 0 0 vreg1 x 0.40 times 0 0 0 0 1 vreg1 x 0.42 times 0 0 0 1 0 vreg1 x 0.44 times : : : : : : 0 1 1 0 0 vreg1 x 0.64 times 0 1 1 0 1 vreg1 x 0.66 times 0 1 1 1 0 vreg1 x 0.68 times 0 1 1 1 1 the internal volume stops, and vcomh can be adjusted from vcomr by an external variable resistor. 1 0 0 0 0 vreg1 x 0.70 times 1 0 0 0 1 vreg1 x 0.72 times 1 0 0 1 0 vreg1 x 0.74 times : : : : : : 1 1 1 0 0 vreg1 x 0.94 times 1 1 1 0 1 vreg1 x 0.96 times 1 1 1 1 0 vreg1 x 0.98 times 1 1 1 1 1 the internal volume stops, and vcomh can be adjusted from vcomr by an external variable resistor. notes: adjust the settings between vreg1 and vcm0 to vcm4 so that the vcomh voltage is lower than gvdd .
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 39 entry mode (r05h) compare register (r06h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 0 0 0 bgr 0 0 hwm 0 0 0 i/d1 i/d0 am lg2 lg1 lg0 w 1 cp15 cp14 cp13 cp12 cp11 cp10 cp9 cp8 cp7 cp6 cp5 cp4 cp3 cp2 cp1 cp0 the write date sent from the microcomputer is modified in the S6D0110 written to the gram. the display data in the gram can be quickly rewritten to reduce the load of the microcomputer software processing. for details, see the graphics operation function section. hwm: when hwm=1, data can be written to the gram at high speed. in high-speed write mode, four words of data are written to the gram in a single operation at the writing to ram four times. write to ram four times, otherwise the four words cannot be written to the gram. thus, set the lower 2 bits to 0 when setting the ram address. for details, see the high speed ram write mode section. i/d1-0: when i/d1-0 = 1, the address counter (ac) is automatically increas ed by 1 after the data is written to the gram. when i/d1-0 = 0, the ac is automatically decreased by 1 after the data is written to the gram. automatic address counter updating is not performed when reading data from gram . the increment/decrement setting of the address counter by i/d1-0 is performed independently for the upper (ad15-8) and lower (ad7-0) addresses. the am bit sets the direction of moving through the addresses when the gram is written. am: set the automatic update method of the ac after the data is written to the gram. when am = 0, the data is continuously written in parallel. when am = 1, the data is continuously written vertically. w h en window address range is specified, the gram in the window address range can be written to according to the i/d1-0 and am settings. table 20 . address direction setting i/d1-0= ? 00 ? h: decrement v: decrement i/d1-0= ? 01 ? h: increment v: increment i/d1-0= ? 10 ? h: decrement v: increment i/d1-0= ? 11 ? h: increment v: increment am=0 horizontal 0000 h af83h 0000 h af83h 0000 h af83h 0000 h af83h am=1 vertical 0000 h af83h af83h 0000 h af83h 0000 h af83h 0000 h
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 40 bgr : when 16-bit data is written to gram, bit-order of the data can be reversed by use of this bit. therefore, bit- order of the data is set to be when bgr is 0, when bgr is 1. please be aware that setting bgr to 1 will convert the order of the cp15-0 and wm15-0 bits in the same way. lg2 ? 0: compare the data read from the gram by the microcomputer with the compare registers (cp7 ? 0) by a compare/logical operation and write the results to gram. for details, see the logical/compare operation function. cp15 ? 0: set the compare register for the compare operation with the data read from the gram or written by the microcomputer. 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 logical operation (with read data and write data) lg2-0 = ? 000 ? : replace lg2-0 = ? 001 ? : or lg2-0 = ? 010 ? : and lg2-0 = ? 011 ? : eor compare operation (with read data and write data) lg2-0 = ? 100 ? : replacement of matched read data lg2-0 = ? 101 ? : replacement of unmatched read data lg2-0 = ? 110 ? : replacement of matched write data lg2-0 = ? 111 ? : replacement of unmatched write data write data mask (wm15-0) gram write data sent from the micro computer (db15-0) logical/compare operation (lg2-0) write data mask* (wm15-0) note: the write data mask (wm11-0) is set by the register in the ram write data mask section figure 9 . logical/compare operation display control (r07h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 0 0 0 pt1 pt0 vle2 vle1 spt 0 0 gon dte cl rev d1 d0 pt1-0: normalize the source outputs when non-displayed area of the partial display is driven. for details, see the screen-division driving function section. vle2 ? 1: when vle1 = 1, a vertical scroll is performed in the 1st screen. when vle2 = 1, a vertical scroll is performed in the 2nd screen. vertical scrolling on the two screens cannot be controlled at the same time. vle2 vle1 2 nd screen 1 st screen 0 0 fixed display fixed display 0 1 fixed display scroll display 1 0 scroll display fixed display 1 1 setting disabled setting disabled
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 41 spt: when spt = 1, the 2-division lcd drive is performed. for details, see the screen-division driving function section. gon: gate off level is set to be vss when gon = 0. when gon= 0 and disptmg= 0, g1 to g176 output is fixed to vss level . when gon= 1, g1 to g176 output is fixed to vgh or vgoff level. see the instruction set up flow for further description on the display on/off flow. gon gate output 0 vgh/vss 1 vgh/vgoff dte: disptmg output is fixed to vss when dte = 0. dte disptmg output 0 halt (vss) 1 operation (vdd/vss) cl: when cl = 1, number of display is 8-color mode. for details, see the 8-color display mode. cl number of display colors 0 65,536 colors 1 8 colors
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 42 rev: displays all character and graphics display sections with reversal when rev = 1. for details, see the reversed display function section. since the grayscale level can be reversed, display of the same data is enabled on normally white and normally black panels. 1) combination with the partial display source output level non-display area display data pt1-0=(0,1) pt1-0=(1,0) pt1-0=(1,1) rev gram data vcom=l vcom=h vcom=l vcom=h vcom=l vcom=h vcom=l vcom=h 0 16 ? h0000 : 16 ? hffff v63 : v0 v0 : v63 v63 v0 vss vss hi-z hi-z 1 16 ? h0000 : 16 ? hffff v0 : v63 v63 : v0 v63 v0 vss vss hi-z hi-z 2) combination with the d1-0 source output level d1-0=(1,1) d1-0=(1,0) d1-0=(0,1) d1-0=(0,0) rev gram data vcom=l vcom=h vcom=l vcom=h vcom=l vcom=h vcom=l vcom=h 0 16 ? h0000 : 16 ? hffff v63 : v0 v0 : v63 v63 v0 vss vss vss vss 1 16 ? h0000 : 16 ? hffff v0 : v63 v63 : v0 v63 v0 vss vss vss vss d1 ? 0: display is on when d1 = 1 and off when d1 = 0. when off, the display data remains in the gram, and can be displayed instantly by setting d1 = 1. when d1 is 0, the display is off with the entire source outputs set to the vss level. because of this, the S6D0110 can control the charging current for the lcd with ac driving. control the display on/off while control gon and dte. for details, see the instruction set up flow. when d1 ? 0 = 01, the internal display of the S6D0110 is performed although the display is off. when d1-0 = 00, the internal display operation halts and the display is off. d1 d0 source output S6D0110 internal display operation master/slave signal (cl1, flm, m, disptmg) 0 0 vss halt halt 0 1 vss operate operate 1 0 unlit display operate operate 1 1 display operate operate notes: 1. writing from the microcomputer to the gram is independent from d1 ? 0. 2. in sleep and standby mode, d1 ? 0 = 00. however, the register contents of d1 ? 0 are not modified.
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 43 blanking period control 1 (r08h) blanking period control 2 (r09h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 0 0 0 0 fp3 fp2 fp1 fp0 0 0 0 0 bp3 bp2 bp1 bp0 w 1 0 0 0 0 blp1 3 blp1 2 blp1 1 blp1 0 blp2 3 blp2 2 blp2 1 blp2 0 0 0 0 0 the blanking period in the front and end of the display area can be defined using this register. when n -raster-row is driving, a blank period is inserted after all screens are drawn. front and back porch can be adjusted using fp3-0 and bp3-0 bits (r08h). in interlace drive mode, blank period can be adjusted using blp13- 0 and blp23-0 bit (r09h). the gram can be quickly rewritten to reduce the load of the microcomputer software processing. for details, see the graphics operation function section. fp3 fp2 fp1 fp0 blanking period bp3 bp2 bp1 bp0 blanking period 0 0 0 0 0 raster-row 0 0 0 0 0 raster-row 0 0 0 1 1 raster-row 0 0 0 1 1 raster-row 0 0 1 0 2 raster-row 0 0 1 0 2 raster-row 0 0 1 1 3 raster-row 0 0 1 1 3 raster-row 0 1 0 0 4 raster-row 0 1 0 0 4 raster-row 0 1 0 1 5 raster-row 0 1 0 1 5 raster-row 0 1 1 0 6 raster-row 0 1 1 0 6 raster-row 0 1 1 1 7 raster-row 0 1 1 1 7 raster-row 1 0 0 0 8 raster-row 1 0 0 0 8 raster-row 1 0 0 1 9 raster-row 1 0 0 1 9 raster-row 1 0 1 0 10 raster-row 1 0 1 0 10 raster-row 1 0 1 1 11raster-row 1 0 1 1 11raster-row 1 1 0 0 12 raster-row 1 1 0 0 12 raster-row 1 1 0 1 13 raster-row 1 1 0 1 13 raster-row 1 1 1 0 14 raster-row 1 1 1 0 14 raster-row 1 1 1 1 15 raster-row 1 1 1 1 15 raster-row blp13 blp12 blp11 blp10 blanking period blp23 blp22 blp21 blp20 blanking period 0 0 0 0 0 raster-row 0 0 0 0 0 raster-row 0 0 0 1 1 raster-row 0 0 0 1 1 raster-row 0 0 1 0 2 raster-row 0 0 1 0 2 raster-row 0 0 1 1 3 raster-row 0 0 1 1 3 raster-row 0 1 0 0 4 raster-row 0 1 0 0 4 raster-row 0 1 0 1 5 raster-row 0 1 0 1 5 raster-row 0 1 1 0 6 raster-row 0 1 1 0 6 raster-row 0 1 1 1 7 raster-row 0 1 1 1 7 raster-row 1 0 0 0 8 raster-row 1 0 0 0 8 raster-row 1 0 0 1 9 raster-row 1 0 0 1 9 raster-row 1 0 1 0 10 raster-row 1 0 1 0 10 raster-row 1 0 1 1 11raster-row 1 0 1 1 11raster-row 1 1 0 0 12 raster-row 1 1 0 0 12 raster-row 1 1 0 1 13 raster-row 1 1 0 1 13 raster-row 1 1 1 0 14 raster-row 1 1 1 0 14 raster-row 1 1 1 1 15 raster-row 1 1 1 1 15 raster-row
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 44 frame cycle control (r0bh) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 no1 no0 sdt1 sdt0 eq1 eq0 div1 div0 0 0 0 0 rtn3 rtn2 rtn1 rtn0 rtn3-0: set the 1h period. rtn3 rtn2 rtn1 rtn0 clock cycles per raster row 0 0 0 0 16 0 0 0 1 17 0 0 1 0 18 . . . . . . . . . . . . . . . 1 1 1 0 30 1 1 1 1 31 div1-0: set the division ratio of clocks for internal operation (div1-0). internal operations are driven by clocks, which are frequency divided according to the div1-0 setting. frame frequency can be adjusted along with the 1h period (rtn3-0). when changing number of the drive cycle, adjust the frame frequency. for details, see the frame frequency adjustment function section. div1 div0 division ratio internal operation clock frequency 0 0 1 fosc/1 0 1 2 fosc/2 1 0 4 fosc/4 1 1 8 fosc/8 *fosc = r-c oscillation frequency eq1-0: eq period is sustained for the number of clock cycle which is set on eq1-0. when vcoml<0, set these bits as ? 00 ? for preventing the abnormal function. eq1 eq0 eq period 0 0 no eq 0 1 1 clock cycle 1 0 2 clock cycle 1 1 3 clock cycle frame frequency = f osc clock cycles per raster-row x division ratio x (line+b) [ hz] f osc : r-c oscillation frequency line: number of raster-rows (nl bit) clock cycles per raster-row: rtn bit division ratio: div bit b: blank period(back porch + front porch) figure 10 . formula for the frame frequency
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 45 sd t 1-0: set delay amount from gate edge (end) to source output. sdt1 sdt0 delay amount of the source output 0 0 1 clock cycle 0 1 2 clock cycle 1 0 3 clock cycle 1 1 4 clock cycle gn 1 h period 1 h period sn eq delay amount of the source output equalizing period figure 11 . set delay from gate output to source output no1-0: set amount of non-overlay for the gate output. no1 no0 amount of non-overlab 0 0 0 clock cycle 0 1 4 clock cycle 1 0 6 clock cycle 1 1 8 clock cycle gn gn +1 1 h period 1 h period non - overlap period cl1 gn gn +1 1 h period 1 h period non - overlap period cl1 figure 12 . non-overlap period
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 46 gate scan position (r0fh) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 no1 0 0 0 0 0 0 0 0 0 0 scn4 scn3 scn2 scn1 scn0 scn 4-0: set the scanning starting position of the gate driver. scanning start position scn4 scn3 scn2 scn1 scn0 gs=0 gs=1 0 0 0 0 0 g1 g176 0 0 0 0 1 g9 g168 0 0 0 1 0 g17 g160 : : : : : : : : : : : : : : 1 0 0 1 1 g153 g24 1 0 1 0 0 g161 g16 1 0 1 0 1 g169 g8 g1 g160 g161 g176 g1 g160 g161 g176 g16 g17 gs = 0 nl = 10010 scn4-0 = 00000 gs = 1 nl = 10010 scn4-0 = 00010 note: set nl4-0 on the gate scan end that does not exceed value 176 figure 13 . relationship between nl and scn set up value
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 47 vertical scroll control (r11h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 0 0 0 0 0 0 0 0 vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 vl7-0: specify scroll length at the scroll display for vertical smooth scrolling. any raster-row from the first to 176 th can be scrolled for the number of the raster-row. after 176 th raster-row is displayed, the display restarts from the first raster-row. the display-start raster-row (vl7-0) is valid when vle1 = 1 or vle2 = 1. the raster-row display is fixed when vle2-1 = 00. vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 scroll length 0 0 0 0 0 0 0 0 0 raster-row 0 0 0 0 0 0 0 1 1 raster-row 0 0 0 0 0 0 1 0 2 raster-row . . . . . . 1 0 1 0 1 1 1 0 174 raster-row 1 0 1 0 1 1 1 1 175 raster-row note: don ? t set any higher raster-row than 175 ( ? af ? h) 1 st screen driving position (r14h) 2 nd screen driving position (r15h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 se17 se16 se15 se14 se13 se12 se11 se10 ss17 ss16 ss15 ss14 ss13 ss12 ss11 ss10 w 1 se27 se26 se25 se24 se23 se22 se21 se20 ss27 ss26 ss25 ss24 ss23 ss22 ss21 ss20 ss17 ? 1 0: specify the driving start position for the first screen in a line unit. the lcd driving starts from the ? set value +1 ? common driver. se17 ? 1 0: specify the driving end position for the first screen in a line unit. the lcd driving is performed to the 'set value + 1' gate driver. for instance, when ss17 ? 10 = 07 h and se17 ? 10 = 10 h are set, the lcd driving is performed from g8 to g17, and black display driving is performed for g1 to g7, g18, and others. ensure that ss17 ? 10 se17 ? 10 af h . for details, see the screen-division driving function section. ss27 ? 1 0: specify the driving start position for the second screen in a line unit. the lcd driving starts from the 'set value + 1' gate driver. the second screen is driven when spt = 1. se27 ? 2 0: specify the driving end position for the second screen in a line unit. the lcd driving is performed to the 'set value + 1' gate driver. for instance, when spt = 1, ss27 ? 20 = 20 h , and se27 ? 20 = af h are set, the lcd driving is performed from g33 to g80. ensure that ss17 ? 10 se17 ? 10 ss27 ? 20 se27 ? 20 afh . for details, see the screen-division driving function section.
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 48 horizontal ram address position (r16h) vertical ram address position (r17h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 hea 7 hea 6 hea 5 hea 4 hea 3 hea 2 hea 1 hea 0 hsa 7 hsa 6 hsa 5 hsa 4 hsa 3 hsa 2 hsa 1 hsa 0 w 1 vea 7 vea 6 vea 5 vea 4 vea 3 vea 2 vea 1 vea 0 vsa 7 vsa 6 vsa 5 vsa 4 vsa 3 vsa 2 vsa 1 vsa 0 hsa7-0/hea7-0: specify the horizontal start/end positions of a window for access in memory. data can be written to the gram from the address specified by hea 7-0 from the address specified by hsa7-0. note that an address must be set before ram is written. ensure 00 h hsa7-0 hea7-0 83 h . vsa7-0/vea7-0: specify the vertical start/end positions of a window for access in memory. data can be written to the gram from the address specified by vea7-0 from the address specified by vsa7-0. note that an address must be set before ram is written. ensure 00 h vsa7-0 vea7-0 afh. window address 0000 h af83h hsa hea vsa vea gram address space window address setting range ? 00 ? h hsa7-0 hea7-0 ? 83 ? h ? 00 ? h vsa7-0 vea7-0 ? af ? h note: 1. ensure that the window address area is within the gram address space 2. in high-speed write mode, data are written to gram in four-words. thus, dummy write operations should be inserted depending on the window address area. for details, see the high-speed burst ram write function section figure 14 . window address setting range
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 49 ram write data mask (r20h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 wm15 wb14 wm13 wm12 wm11 wm10 wm9 wm8 wm7 wm6 wm5 wm4 wm3 wm2 wm1 wm0 wm15 ? 0: in writing to the gram, these bits mask writing in a bit unit. when wm15 = 1, this bit masks the write data of db1 5 and does not write to the gram. similarly, the wm1 4 to 0 bits mask the write data of db1 4 to 0 in a bit unit. for details, see the graphics operation function section. ram address set (r21h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ad15 ? 0: initially set gram addresses to the address counter (ac). once the gram data is written, the ac is automatically updated according to the am and i/d bit settings. this allows consecutive accesses without resetting address. once the gram data is read, the ac is not automatically updated. gram address setting is not allowed in the standby mode. ensure that the address is set within the specified window address ad15 to ad0 gram setting ? 0000h ? to ? 0083 ? h bitmap data for g1 ? 0100h ? to ? 0183 ? h bitmap data for g2 ? 0200h ? to ? 0283 ? h bitmap data for g3 ? 0300h ? to ? 0383 ? h bitmap data for g4 : : : : : : ? ac00h ? to ? ac83 ? h bitmap data for g173 ? ad00h ? to ? ad83 ? h bitmap data for g174 ? ae00h ? to ? ae83 ? h bitmap data for g175 ? af00h ? to ? af83 ? h bitmap data for g176
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 50 write data to gram (r22h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 wd15 wd14 wd13 wd12 wd11 wd10 wd9 wd8 wd7 wd6 wd5 wd4 wd3 wd2 wd1 wd0 wd15-0: write 16-bit data to the gram. this data selects the grayscale level. after a write, the address is automatically updated according to am and i/d bit settings. during the standby mode, the gram cannot be accessed. db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 wd15 wd14 wd13 wd12 wd11 wd10 wd9 wd8 wd7 wd6 wd5 wd4 wd3 wd2 wd1 wd0 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 1 pixel figure 15 . write data to gram table 21 . gram data and grayscale level gram data setup selected grayscale gram data setup selected grayscale gram data setup selected grayscale gram data setup selected grayscale g r/b n p g r/b n p g r/b n p g r/b n p 000000 00000 v0 v63 010000 01000 v16 v47 100000 - v32 v31 110000 - v48 v15 000001 - v1 v62 010001 - v17 v46 100001 10000 v33 v30 110001 11000 v49 v14 000010 00001 v2 v61 010010 01001 v18 v45 100010 - v34 v29 110010 - v50 v13 000011 - v3 v60 010011 - v19 v44 100011 10001 v35 v28 110011 11001 v51 v12 000100 00010 v4 v59 010100 01010 v20 v43 100100 - v36 v27 110100 - v52 v11 000101 - v5 v58 010101 - v21 v42 100101 10010 v37 v26 110101 11010 v53 v10 000110 00011 v6 v57 010110 01011 v22 v41 100110 - v38 v25 110110 - v54 v9 000110 - v7 v56 010110 - v23 v40 100110 10011 v39 v24 110110 11011 v55 v8 001000 00100 v8 v55 011000 01100 v24 v39 101000 - v40 v23 111000 - v56 v7 001001 - v9 v54 011001 - v25 v38 101001 10100 v41 v22 111001 11100 v57 v6 001010 00101 v10 v53 011010 01101 v26 v37 101010 - v42 v21 111010 - v58 v5 001011 - v11 v52 011011 - v27 v36 101011 10101 v43 v20 111011 11101 v59 v4 001100 00110 v12 v51 011000 01100 v28 v35 101100 - v44 v19 111100 - v60 v3 001101 - v13 v50 011001 - v29 v34 101101 10110 v45 v18 111101 11110 v61 v2 001100 00110 v14 v49 011010 01101 v30 v33 101100 - v46 v17 111110 - v62 v1 001101 - v15 v48 011011 - v31 v32 101101 10111 v47 v16 111111 11111 v63 v0
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 51 read data from gram (r22h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 r 1 rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 rd11 ? 0: read 16-bit data from the gram. when the data is read to the microcomputer, the first-word read immediately after the gram address setting is latched from the gram to the internal read-data latch. the data on the data bus (db15 ? 0) becomes invalid and the second-word read is normal. when bit processing, such as a logical operation, is performed within the S6D0110, only one read can be processed since the latched data in the first word is used. sets the i/d, am, hsa/hea, and vsa/vea bits address: n set dummy read (invalid data) gram -> read data latch read (data of address n) read data latch -> db15-0 address: m set dummy read (invalid data) gram -> read data latch read (data of address m) read-data latch -> db15-0 sets the i/d, am, hsa/hea, and vsa/vea bits address: n set dummy read (invalid data) gram -> read data latch write (data of address n) db15-0 -> gram automatic address update: n+ a dummy read (invalid data) gram -> read data latch write (data of address n+ a ) db15-0 -> gram first word second word first word second word first word second word first word second word i) data read to the microcomputer ii) logical operation processing in S6D0110 figure 16 . gram read sequence
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 52 gamma control (r30h to r37h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w 1 0 0 0 0 0 pkp 12 pkp 11 pkp 10 0 0 0 0 0 pkp 02 pkp 01 pkp 00 w 1 0 0 0 0 0 pkp 32 pkp 31 pkp 30 0 0 0 0 0 pkp 22 pkp 21 pkp 20 w 1 0 0 0 0 0 pkp 52 pkp 51 pkp 50 0 0 0 0 0 pkp 42 pkp 41 pkp 40 w 1 0 0 0 0 0 prp 12 prp 11 prp 10 0 0 0 0 0 prp 02 prp 01 prp 00 w 1 0 0 0 0 0 pkn 12 pkn 11 pkn 10 0 0 0 0 0 pkn 02 pkn 01 pkn 00 w 1 0 0 0 0 0 pkn 32 pkn 31 pkn 30 0 0 0 0 0 pkn 22 pkn 21 pkn 20 w 1 0 0 0 0 0 pkn 52 pkn 51 pkn 50 0 0 0 0 0 pkn 42 pkn 41 pkn 40 w 1 0 0 0 0 0 prn 12 prn 11 prn 10 0 0 0 0 0 prn 02 prn 01 prn 00 pkp52 ? 00: gamma micro adjustment register for the positive polarity output prp12-00: gradient adjustment register for the positive polarity output pkn52-00: gamma micro adjustment register for the negative polarity output prn12-00: gradient adjustment register for the negative polarity output for details, see the gamma adjustment function.
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 53 reset function the S6D0110 is internally initialized by reset input. the reset input must be held for at least 1 ms. do not access the gram or initially set the instructions until the r-c oscillation frequency is stable after power has been supplied (10 ms). instruction set initialization 1. start oscillation executed 2. driver output control (nl4 ? 0 = 10101, ss = 0, cs = 0) 3. b-pattern waveform ac drive (fld1-0 = 01, b/c = 0, eor = 0, nw5 ? 0 = 00000) 4. power control 1 (sap2-0 = 000, bt2-0 = 000, dc2 ? 0 = 000, ap2 ? 0 = 000: lcd power off, slp = 0, stb = 0: standby mode off) 5. power control 2 (cad = 0, vrn4-0 = 0000 0 , vrp4-0 = 0000 0) 6. entry mode set (hwm = 0, i/d1-0 = 11: increment by 1, am = 0: horizontal move, lg2 ? 0 = 000: replace mode) 7. compare register (cp15 ? 0: 0000000000000000) 8. display control (pt1-0 = 00, vle2 ? 1 = 00: no vertical scroll, spt = 0, gon = 0, dte = 0, cl = 0: 65536 color mode, rev = 0, d1 ? 0 = 00: display off) 9. display control (fp3-0=0101, bp3-0=0011, blp13-0=0010, blp23-0=0010) 10 . frame cycle control (no1-0 = 00, sdt1-0 = 00, eq1-0 = 00: no equalizer, div1-0 = 00: 1-divided clock, rtn3-0 = 0000: 16 clock cycle in 1h period) 1 1 . power control 3 (vc2-0 = 000) 1 2 . power control 4 (vrl3-0 = 0000, pon=0, vrh 3 -0 = 0000 ) 1 3 . power control 5 (vcomg = 0, vdv4-0 = 00000, vcm4-0 = 00000 ) 1 4 . gate scanning starting position (scn4-0 = 00000) 1 5 . vertical scroll (vl7 ? 0 = 0000000) 1 6. 1st screen division (se17-10 = 11111111, ss17-10 = 00000000) 1 7 . 2nd screen division (se27-20 = 11111111, ss27-20 = 00000000) 1 8 . horizontal ram address position (hea7-0 = 10000011, hsa7-0 = 00000000) 1 9 . vertical ram address position (vea7-0 = 101011 1 1, vsa7-0 = 00000000) 20 . ram write data mask (wm15 ? 0 = 0000 h : no mask) 2 1 . ram address set (ad15 ? 0 = 0000 h ) 2 2 . gamma control (pkp02 ? 00 = 000, pkp12 ? 10 = 000, pkp22 ? 20 = 000, pkp32 ? 30 = 000, pk42 ? 40 = 000, pkp52 ? 50 = 000, prp02 ? 00 = 000, prp12 ? 10 = 000) (pkn02 ? 00 = 000, pkn12 ? 10 = 000, pkn22 ? 20 = 000, pkn32 ? 30 = 000, pkn42 ? 40 = 000, pkn52 ? 50 = 000, prn02 ? 00 = 000, prn12 ? 10 = 000) gram data initialization gram is not automatically initialized by reset input but must be initialized by software while display is off (d1 ? 0 = 00). output pin initialization 1. lcd driver output pins (source output ) : output vss level (gate output) : output vgoff level 2. oscillator output pin (osc2): outputs oscillation sign
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 54 voltage regulation function the S6D0110 have internal voltage regulator. voltage regulation function is controlled by pregb pin. if pregb= ? h ? , voltage regulation is stopped. pregb= ? l ? enables internal voltage regulation function. by use of this function, internal logic circuit damage can be prohibited. furthermore , power consumption also be obtained. detailed function description and application setup is described in the following diagram. voltage regulator internal vdd (1.9v) vdd3 (external power) range: 2.5~3.3v rvdd pregb pregb= 'l' : regulator on vdd input level shifter internal vdd internal logic gnd (a) voltage regulation function enabled voltage regulator internal vdd input pregb level shifter internal vdd internal logic vdd (external power) 1.8~2.5v vdd3 rvdd pregb= 'h' : regulator off (b) voltage regulation function disabled figure 13. voltage regulation function
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 55 system interface system interface mode of S6D0110 can be fixed by use of im2/1/0 pin. instruction setting and gram access is executed via system interface. table 22 . im bits and system interface im2 im1 im0 system interface db pin 0 0 0 68-system 16-bit interface db15 ~ 0 0 0 1 68-system 8-bit interface db15 ~ 8 0 1 0 80-system 16-bit interface db15 ~ 0 0 1 1 80-system 8-bit interface db15 ~ 8 1 0 * serial peripheral interface (spi) db1 ~ 0 1 1 * setting disabled - * * * setting disabled - parallel data transfer 16-bit bus interface setting the im2/1/0 (interface mode) to the vss / vss / vss level allows 68-system e-clock-synchronized 16-bit parallel data transfer. setting the im2/1/0 to the vss /vdd3/ vss level allows 80-system 16-bit parallel data transfer. when the number of bus or the mounting area is limited, use an 8-bit bus interface. mpu csn a1 /wr / rd d15-d0 S6D0110 csb rs /wr / rd db15-db0 16 figure 17 . interface to 16-bit microcomputer
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 56 8-bit bus interface setting the im2/1/0 (interface mode) to the vss/vss /vdd3 level allows 68-system e-clock-synchronized 8-bit parallel data transfer using pins db15 ? db8. setting the im 2/ 1/0 to the vss/ vdd3/vdd3 level allows 80-system 8- bit parallel data transfer. the 16-bit instructions and ram data are divided into upper/lower eight bit s and the transfer starts from the upper eight bits. fix unused pins db7 ? db0 to the vdd3 or vss level. note that the upper bytes must also be written when the index register is written. mpu csn a1 /wr /rd d7-d0 S6D0110 csb rs /wr / rd db15-db8 8 db7-db0 8 figure 18 . interface to 8-bit microcomputer note: the S6D0110 supports the transfer synchronization function, which resets the upper/lower counter to count upper/lower 8-bit data transfer in the 8-bit bus interface. noise causing transfer mismatch between the eight upper and lower bits can be corrected by a reset triggered by consecutively writing a 00h instruction four times. the next transfer starts from the upper eight bits. executing synchronization function periodically can recover any runaway in the display system ? 00 ? h ? 00 ? h ? 00 ? h ? 00 ? h upper or lower upper lower (1) (2) (3) (4) 8- bit transfer synchronization rs r/w e db15 to db8 figure 19 . 8-bit transfer synchronization
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 57 serial data transfer setting the im 2/ 1 pin to the vdd3/vss level allows serial peripheral interface (spi) transfer, using the chip select line (cs*), serial transfer clock line (scl), serial input data (sdi), and serial output data (sdo). for a serial interface, the im0/id pin function uses an id pin. if the chip is set up for serial interface, the db15-2 pins that are not used must be fixed at vdd3 or vss . the S6D0110 initiates serial data transfer by transferring the start byte at the falling edge of cs* input. it ends serial data transfer at the rising edge of cs* input. the S6D0110 is selected when the 6-bit chip address in the start byte matches the 6-bit device identification code that is assigned to the S6D0110 . w hen selected, the S6D0110 receives the subsequent data string. the lsb of the identification code can be determined by the id pin. the five upper bits must be 011 1 0. two different chip addresses must be assigned to a single S6D0110 because the seventh bit of the start byte is used as a register select bit (rs): that is, when rs = 0, data can be written to the index register or status can be read, and when rs = 1, an instruction can be issued or data can be written to or read from ram. read or write is selected according to the eighth bit of the start byte (r/w bit). the data is received when the r/w bit is 0, and is transmitted when the r/w bit is 1. after receiving the start byte, the S6D0110 receives or transmits the subsequent data byte-by-byte. the data is transferred with the msb first. all S6D0110 instructions are 16 bits. two bytes are received with the msb first (db15 to 0), then the instructions are internally executed. after the start byte has been received, the first byte is fetched as the upper eight bits of the instruction and the second byte is fetched as the lower eight bits of the instruction. four bytes of ram read data after the start byte are invalid. the S6D0110 starts to read correct ram data from the fifth byte. table 23 . start byte format transfer bit s 1 2 3 4 5 6 7 8 device id code rs r/w start byte format transfer start 0 1 1 1 0 id note: id bit is selected by the im0/id pin. table 24 . rs and r/w bit function rs rw function 0 0 set index register 0 1 read status 1 0 writes instruction or ram data 1 1 reads instruction or ram data
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 58 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0 1 1 1 0 id r rw db db db db db db db db db db db db db db db db 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 device id rs r/w start byte index register setting instruction ram data write db db db db db db db db db db db db db db db db 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 status read instruction read ram data read a) timing basic data transfer through clock synchronized serial bus interface transfer start transfer end b) timing of consecutive data-transfer through clock-synchronized serial bus interface start byte instruction 1: upper instruction 2: lower instruction 2: upper 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 instruction 1: execution time end start note: the first byte after the start byte is always the upper eight bits. scl (input) sdi (input) sdo (output) scl (input) sdi (input) cs* (input) cs* (input) c) ram-data read-transfer timing start byte rs=1 r/w=1 dummy read 1 dummy read 2 dummy read 3 dummy read 4 dummy read 5 ram read: upper 8-bits ram read: lower 8-bits start end note: 5-byte of ram read data after the start byte are invalid. the S6D0110 starts to read the correct ram data from sixth byte scl (input) sdi (input) sdo (output) cs* (input) figure 20 . procedure for transfer on clock synchronized serial bus interface
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 59 cs* (input) start byte rs=1 r/w=1 sdi (input) dummy read 1 status read upper 8-bit status read lower 8-bit start end note: 2-byte of the ram read after the start byte is invalid. the S6D0110 starts to read the correct ram data from the third data. d) status read/instruction read sdo (output) figure 21 . procedure for transfer on clock synchronized serial bus interface (continued)
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 60 high-speed burst ram write function the S6D0110 has a high-speed burst ram-write function that can be used to write data to ram in one-fourth the access time required for an equivalent standard ram-write operation. this function is especially suitable for applications that require the high-speed rewriting of the display data, for example, display of color animations, etc. when the high-speed ram-write mode (hwm) is selected, data for writing to ram is once stored to the S6D0110 internal register. when data is selected four times per word, all data is written to the on-chip ram. while this is taking place, the next data can be written to an internal register so that high-speed and consecutive ram writing can be executed for animated displays, etc. microcomputer register 1 register 2 register 3 register 4 16 64 ? 0000 ? h ? 0001 ? h ? 0002 ? h ? 0003 ? h gram address counter (ac) 16 a) high-speed burst ram write operation flow cs* (input) b) example of the operation of high-speed consecutive writing to ram 1 2 3 4 1 2 3 4 1 2 3 4 index (r22) ram data 1 ram data 2 ram data 3 ram data 4 ram data 5 ram data 6 ram data 7 ram data 8 ram data 9 ram data 10 ram data 11 ram data 12 index ram write execution time ram write execution time ram write execution time* ram data 1 to 4 ram data 5 to 8 ram data 9 to 12 e (input) db15-0 (input/output) ram write data (64 bits) ram address (ac 15-0) ? 0000 ? h ? 0004 ? h ? 0008 ? h ? 000 a ? h figure 22 . example of the operation of high-speed consecutive writing to ram
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 61 when high-speed write mode is used, note the following. 1. the logical and compare operations cannot be used. 2. data is written to ram each four words. when an address is set, the lower two bits in the address must be set to the following values. *when id0=0, the lower two bits in the address must be set to 11 and be written to ram. *when id0=1, the lower two bits in the address must be set to 00 and be written to ram. 3. data is written to ram each four words. if less than four words of data is written to ram, the last data will not be written to ram. 4. when the index register and ram data write (r22h) have been selected, the data is always written first. ram cannot be written to and read from at the same time. hwm must be set to 0 while ram is being read. 5. high-speed and normal ram write operations cannot be executed at the same time. the mode must be switched and the address must then be set. 6. when high-speed ram write is used with a window address-range specified, dummy write operation may be required to suit the window address range-specification. refer to the high-speed ram write in the window address section. table 25 . comparison between normal and high-speed ram write operations normal ram write (hwm=0) high-speed ram write (hwm=1) logical operation function can be used cannot be used compare operation function can be used cannot be used swap function can be used can be used write mask function can be used can be used ram address set can be specified by word id0 bit=0: set the lower two bits to 11 id0 bit=1: set the lower two bits to 00 ram read can be read by word cannot be used ram write can be written by word dummy write operations may have to be inserted according to a window address-range specification window address can be set by word can be set by word note: 1 word = 2 byte.
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 62 high-speed ram write in the window address when a window address range is specified, gram data that is in an optional window area can be updated quickly and continuously by use of dummy write operation . so that the number of ram access become 4n as shown in the table below. dummy write operation must be inserted a t the first or last of a row of data, depending on the horizontal window- address range specification bits (hsa1 to 0, hea1 to 0). numbers of dummy write operations of a row must be 4n. table 26 . number of dummy write operations in high-speed ram write ( hs a bits) hsa1 hsa0 number of dummy write operations to be inserted at the start of a row 0 0 0 0 1 1 1 0 2 1 1 3 table 27 . table 28 . number of dummy write operations in high-speed ram write ( he a bits) hea1 hea0 number of dummy write operations to be inserted at the end of a row 0 0 3 0 1 2 1 0 1 1 1 0 note: each row of access must consist of 4 x n operations, including the dummy writes. horizontal access count = first dummy write count + write data count + last dummy write count = 4 x n
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 63 an example of high-speed ram write with a window address-range specified is shown below. the window address-range can be accessed consecutively and quickly by inserting two dummy writes at the start of a row and three dummy writes at the end of a row, as determined by using the window address-range specification bits (hsa1 to 0 =10, hea1 to 0 =00). writing in the horizontal direction am=0, id0=1 window address-range setting hsa=h12, hea=h30 vsa=h08, vea=ha0 high-speed ram write mode setting hwm=1 address set ad=h0810* dummy ram write x 2 ram write x 31 dummy ram write x 3 x 153 h0000 haf83 window address range specification ( rewritable area) h0812 ha030 window address-range setting hsa=h12, hea=h30 vsa=h08, vea=ha0 note: the address set for the high-speed ram write must be 00 or 11 according to the value of the id0 bit. only pre-specified window address-range will be overwritten. gram address map figure 23 . example of high-speed ram write with a window address-range specification
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 64 window address function when data is written to the on-chip gram, a window address-range which is specified by the horizontal address register (start: hsa7-0, end: hea 7-0) and vertical address register (start: vsa7-0, end: vea7-0) can be updated consecutively . data is written to addresses in the direction specified by the am and id1-0 bit. when image data, etc. is being written, data can be written consecutively without thinking a data wrap by doing this. the window must be specified to be within the gram address area described as following example. addresses must be set within the window address. [restriction on window address-range settings] (horizontal direction) 00h hsa7-0 hea7-0 83 h (vertical direction) 00h vsa7-0 vea7-0 af h [restriction on address settings during the window address] (ram address) hsa7-0 ad7-0 hea7-0 vsa7-0 ad15-8 vea7-0 note: in high-speed ram-write mode, the lower two bits of the address must be set as shown below according to the value of the id0 bit. id 0 =0: the lower two bits of the address must be set to 11. id 0 =1: the lower two bits of the address must be set to 00. gram address map ? 0000 ? h ? 0083 ? h ? af00 ? h ? af83 ? h ? 2010 ? h ? 2110 ? h ? 5f10 ? h ? 202 f ? h ? 212f ? h ? 5f2f ? h window address-range specification area hsa7-0 = ? 10 ? h, hse7-0 = ? 2f ? h i/d = 1 (increment) vsa7-0 = ? 20 ? h, vea7-0 = ? 5f ? h am = 0 (horizontal writing) figure 24 . example of address operation in the window address specification
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 65 graphics operation function the S6D0110 can greatly reduce the load of the microcomputer graphics software processing through the 16-bit bus architecture and internal graphics-bit operation function. this function supports the following: 1. a write data mask function that selectively rewrites some of the bits in the 16-bit write data. 2. a logical operation write function that writes the data sent from the microcomputer and the original ram data by a logical operation. 3. a conditional write function that compares the original ram data or write data and the compare-bit data and writes the data sent from the microcomputer only when the conditions match. even if the display size is large, the display data in the graphics ram (gram) can be quickly rewritten. the graphics bit operation can be controlled by combining the entry mode register, the bit set value of the ram- write-data mask register, and the read/write from the microcomputer. table 29 . graphics operation bit setting operation mode i/d am lg2-0 operation and usage write mode 1 0/1 0 000 horizontal data replacement, horizontal-border drawing write mode 2 0/1 1 000 vertical data replacement, vertical-border drawing write mode 3 0/1 0 110 111 conditional horizontal data replacement, horizontal- border drawing write mode 4 0/1 1 110 111 conditional vertical data replacement, vertical-border drawing read/write mode 1 0/1 0 001 010 011 horizontal data write with logical operation, horizontal- border drawing read/write mode 2 0/1 1 001 010 011 vertical data write with logical operation, vertical- border drawing read/write mode 3 0/1 0 100 101 conditional horizontal data replacement, horizontal- border drawing read/write mode 4 0/1 1 100 101 conditional vertical data replacement, vertical-border drawing
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 66 microcomputer write-data latch read-data latch logical/compare operation (lg2- 0): 000:replacement,001:or,010:and,011:eor, 100:replacement with matched read, 101:replacement with unmatched read, 110:replacement with matched write, 111:replacement with unmatched write logical operation bit (lg2=0) compare bit (cp15-0) write-mask register (wm15-0) write bit mask graphic ram (gram) address counter (ac) +1/-1 +256 16 16 16 16 16 16 16 16 3 figure 25 . data processing flow of graphic operation
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 67 write-data mask function the S6D0110 has a bit-wise write-data mask function that controls writing the two-byte data from the microcomputer to the gram. bits that are 0 in the write-data mask register (wm15 ? 0) cause the corresponding db bit to be written to the gram. bits that are 1 prevent writing to the corresponding gram bit to the gram; the data in the gram is maint ained. this function can be used when only one-pixel data is rewritten or the particular display color is selectively rewritten. r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 db15 db0 db15 db0 wm15 wm0 data from the microcomputer write data mask gram data 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 * * * * * g05 g04 g03 g02 g01 g00 * * * * * figure 26 . example of write-data mask function operation
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 68 graphics operation processing 1. write mode 1: am = 0, lg2 ? 0 = 000 this mode is used when the data is horizontally written at high speed. it can also be used to initialize the graphics ram (gram) or to draw borders. the write-data mask function (wm15 ? 0) is also enabled in these operations. after writing, the address counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edge of the gram. 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 wm15 wm0 db15 db0 1 1 0 0 0 * * * * * * * * * * * 1 0 0 1 1 * * * * * * * * * * * operation examples: 1) i/d = ? 1 ? , am = ? 0 ? , lg2-0 = ? 000 ? 2) wm15-0 = ? 07ff ? h 3) ac = ? 0000 ? h write data mask: write data (1): write data (2): ? 0000 ? h ? 0001 ? h ? 0002 ? h write data (1) write data (2) gram note: the bits in the gram, * ? s, are not changed figure 27 . writing operation of write mode 1
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 69 2. write mode 2: am = 1, lg2-0 = 000 this mode is used when the data is vertically written at high speed. it can also be used to initialize the gram, develop the font pattern in the vertical direction, or draw borders. the write-data mask function (wm15 ? 0) is also enabled in these operations. after writing, the address counter (ac) automatically increments by 256, and automatically jumps to the upper-right edge (i/d = 1) or upper-left edge (i/d = 0) following the i/d bit after it has reached the lower edge of the gram. 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 wm15 wm0 db15 db0 1 1 0 0 0 * * * * * * * * * * * 1 0 0 1 1 * * * * * * * * * * * operation examples: 1) i/d = ? 1 ? , am = ? 1 ? , lg2-0 = ? 000 ? 2) wm15-0 = ? 07ff ? h 3) ac = ? 0000 ? h write data mask: write data (1): write data (2): ? 0000 ? h ? 0100 ? h ? 0200 ? h write data (1) write data (2) gram write data (3) 0 1 1 1 1 * * * * * * * * * * * 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 write data (3): note: 1. the bits in the gram, * ? s, are not changed. 2. after writing to address ? af00 ? h, the ac jumps to ? 0001 ? h figure 28 . writing operation of write mode 2
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 70 3. write mode 3: am = 0, lg2-0 = 110/111 this mode is used when the data is horizontally written by comparing the write data and the set value of the compare register (cp15 ? 0). when the result of the comparison in a byte unit satisfies the condition, the write data sent from the microcomputer is written to the gram. in this operation, the write-data mask function (wm15 ? 0) is also enabled. after writing, the address counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edge of the gram. operation examples: 1) i/d = ? 1 ? , am = ? 0 ? , lg2-0 = ? 110 ? 2) cp15-0 = ? 2860 ? h 3) wm15-0 = ? 0000 ? h 4) ac = ? 0000 ? h write data mask: wm15 wm0 compare register: cp15 cp0 write data (1): write data (2): db15 db0 db15 db0 ( matched) ( unmatched) c r c r compare operation compare operation conditional replacement conditional replacement replacement ? 0000 ? h ? 0001 ? h gram matched replacement of write data (1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 * * * * * * * * * * * * * * * * 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 * * * * * * * * * * * * * * 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 figure 29 . writing operation write mode 3
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 71 4. write mode 4: am =1, lg2-0 = 110/111 this mode is used when a vertical comparison is performed between the write data and the set value of the compare register (cp15 ? 0) to write the data. when the result by the comparison in a byte unit satisfies the condition, the write data sent from the microcomputer is written to the gram. in this operation, the write-data mask function (wm15 ? 0) are also enabled. after writing, the address counter (ac) automatically increments by 256, and automatically jumps to the upper-right edge (i/d = 1) or upper-left edge (i/d = 0 ) after it has reached the lower edge of the gram. 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 operation examples: 1) i/d = ? 1 ? , am = ? 1 ? , lg2-0 = ? 111 ? 2) cp15-0 = ? 2860 ? h 3) wm15-0 = ? 0000 ? h 4) ac = ? 0000 ? h write data mask: wm15 wm0 compare register: cp15 cp0 write data (1): write data (2): db15 db0 db15 db0 ( unmatched) ( matched) c r c r compare operation compare operation conditional replacement conditional replacement replacement ? 0000 ? h ? 0100 ? h ? af00 ? h write data (1) write data (2) gram note: 1. the bits in the gram, * ? s, are not changed. 2. after writing to address ? af00 ? h, the ac jumps to ? 0001 ? h ? 0000 ? h ? 0001 ? h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 figure 30 . writing operation of write mode 4
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 72 5. read/write mode 1: am = 0, lg2-0 = 001/010/011 this mode is used when the data is horizontally written at high speed by performing a logical operation with the original data. it reads the display data (original data), which has already been written in the gram, performs a logical operation with the write data sent from the microcomputer, and rewrites the data to the gram. this mode reads the data during the same access-pulse width (68-system: enabled high level, 80-system: rd* low level) as the write operation since reading the original data does not latch the read data into the microcomputer but temporarily holds it in the read-data latch. however, the bus cycle requires the same time as the read operation. the write-data mask function (wm15 ? 0) is also enabled in these operations. after writing, the address counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edges of the gram. operation examples: 1) i/d = ? 1 ? , am = ? 0 ? , lg2-0 = ? 001 ? (or) 2) wm15-0 = ? 0000 ? h 3) ac = ? 0000 ? h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 write data mask: wm15 wm0 1 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 write data (1): write data (2): read data (1): read data (2): 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 db15 db0 logical operation(or) logical operation(or) 1 0 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 ? 0000 ? h ? 0001 ? h gram 1 0 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 read data(1) + write data (1) read data(2) + write data (2) figure 31 . writing operation of read/write mode 1
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 73 6. read/write mode 2: am = 1, lg1-0 = 001/010/011 this mode is used when the data is vertically written at high speed by performing a logical operation with the original data. it reads the display data (original data), which has already been written in the gram, performs a logical operation with the write data sent from the microcomputer, and rewrites the data to the gram. this mode can read the data during the same access-pulse width (68-system: enabled high level, 80-system: rd* low level) as for the write operation since the read operation of the original data does not latch the read data into the microcomputer and temporarily holds it in the read-data latch. however, the bus cycle requires the same time as the read operation. the write-data mask function (wm15 ? 0) is also enabled in these operations. after writing, the address counter (ac) automatically increments by 256, and automatically jumps to the upper-right edge (i/d = 1) or upper-left edge (i/d = 0) following the i/d bit after it has reached the lower edge of the gram. operation examples: 1) i/d = ? 1 ? , am = ? 1 ? , lg2-0 = ? 001 ? (or) 2) wm15-0 = ? ffe0 ? h 3) ac = ? 0000 ? h write data mask: wm15 wm0 1 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 write data (1): write data (2): read data (1): read data (2): 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 db15 db0 logical operation(or) logical operation(or) 1 0 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 ? 0000 ? h ? 0100 ? h ? af00 ? h read data (1) + write data (1) read data (2) + write data (2) gram note: 1. the bits in the gram, * ? s, are not changed. 2. after writing to address ? af00 ? h, the ac jumps to ? 0001 ? h ? 0000 ? h ? 0001 ? h * * * * * * * * * * * 1 1 1 1 1 * * * * * * * * * * * 0 0 0 0 0 figure 32 . writing operation of read/write mode 2
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 74 7. read/write mode 3: am = 0, lg2-0 = 100/101 this mode is used when the data is horizontally written by comparing the original data and the set value of compare register (cp15 ? 0). it reads the display data (original data), which has already been written in the gram, compares the original data and the set value of the compare register in byte units, and writes the data sent from the microcomputer to the gram only when the result of the comparison satisfies the condition. this mode reads the data during the same access-pulse width (68-system: enabled high level, 80-system: rd* low level) as write operation since reading the original data does not latch the read data into the microcomputer but temporarily holds it in the read-data latch. however, the bus cycle requires the same time as the read operation. the write-data mask function (wm15 ? 0) is also enabled in these operations. after writing, the address counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edges of the gram. operation examples: 1) i/d = ? 1 ? , am = ? 0 ? , lg2-0 = ? 100 ? 2) cp15-0 = ? 2860 ? h 3) wm15-0 = ? 0000 ? h 4) ac = ? 0000 ? h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 write data mask: wm15 wm0 compare register: 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 cp15 cp0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 read data (1): read data (2): db15 db0 db15 db0 (matched) (unmatched) c c compare operation compare operation conditional replacement conditional replacement replacement 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 r write data (1): r 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 ? 0000 ? h ? 0001 ? h gram matched replacement of write data (1) 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 write data (2): figure 33 . writing operation of read/write mode 3
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 75 8. read/write mode 4: am =1, lg2-0 = 100/101 this mode is used when the data is vertically written by comparing the original data and the set value of the compare register (cp15 ? 0). it reads the display data (original data), which has already been written in the gram, compares the original data and the set value of the compare register in byte units, and writes the data sent from the microcomputer to the gram only when the result of the compare operation satisfies the condition. this mode reads the data during the same access-pulse width (68-system: enabled high level, 80-system: rd* low level) as the write operation since reading the original data does not latch the read data into the microcomputer but temporarily holds it in the read-data latch. however, the bus cycle requires the same time as the read operation. the write-data mask function (wm15 ? 0) is also enabled in these operations. after writing, the address counter (ac) automatically increments by 256, and automatically jumps to the upper-right edge (i/d = 1) or upper-left edge (i/d = 0) following the i/d bit after it has reached the lower edge of the gram. operation examples: 1) i/d = ? 1 ? , am = ? 1 ? , lg2-0 = ? 101 ? 2) cp15-0 = ? 2860 ? h 3) wm15-0 = ? 0000 ? h 4) ac = ? 0000 ? h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 write data mask: wm15 wm0 compare register: 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 cp15 cp0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 read data (1): read data (2): db15 db0 db15 db0 (matched) (unmatched) c c compare operation compare operation conditional replacement conditional replacement replacement 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 r write data (1): r 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 write data (2): 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 1 1 1 1 1 ? 0000 ? h ? 0100 ? h ? af00 ? h write data (1) write data (2) gram note: 1. the bits in the gram, * ? s, are not changed. 2. after writing to address ? af00 ? h, the ac jumps to ? 0001 ? h ? 0000 ? h ? 0001 ? h 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 figure 34 . writing operation of read/write mode 4
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 76 gate driver scan mode setting gate scan mode of S6D0110 is set by sm and gs bit. gs bit determines the scan direction whether the gate driver scans forward or reverse direction. sm bit determines the method of display division ( even/odd or upper/lower division drive). using this function, various connections between S6D0110 and the liquid crystal panels can be accomplished figure 35 . scan mode setting sm gs scan mode 0 0 g1 g175 g2 g176 odd even tft panel g1 g175 g176 g2 S6D0110 g1 g2 g3 g4 g173 g174 g175 g176 0 1 S6D0110 g1 g175 g176 g2 g1 g175 g2 g176 odd even tft panel g174 g175 g176 g173 g4 g1 g2 g3 1 0 g1 g175 g2 g176 tft panel g1 g175 g176 g2 S6D0110 g1 g3 g5 g173 g175 g2 g4 g6 g174 g176 1 1 g1 g175 g2 g176 tft panel g1 g175 g176 g2 S6D0110 g176 g174 g172 g4 g2 g175 g173 g171 g3 g1
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 77 gamma adjustment function the S6D0110 provides the gamma adjustment function to display 65,536 colors simultaneous ly. the gamma adjustment executed by the gradient adjustment register and the micro-adjustment register that determines 8 grayscale levels. furthermore, since the gradient adjustment register and the micro-adjustment register have the positive polarities and negative polarities, adjust them to match lcd panel respectively. r04 r03 r02 r01 r00 g05 g04 g03 g02 g01 g00 b04 b03 b02 b01 b00 graphics ram (gram) msb lsb 32-grayscale control 64-grayscale control 32-grayscale control lcd driver lcd driver lcd driver r g b lcd grayscale amplifier 64 v0 v63 pkp02 pkp01 pkp00 pkp12 pkp11 pkp10 pkp22 pkp21 pkp20 pkp32 pkp31 pkp30 pkp42 pkp41 pkp40 pkp52 pkp51 pkp50 prp02 prp01 prp00 prp12 prp11 prp10 pkn02 pkn01 pkn00 pkn12 pkn11 pkn10 pkn22 pkn21 pkn20 pkn32 pkn31 pkn30 pkn42 pkn41 pkn40 pkn52 pkn51 pkn50 prn02 prn01 prn00 prn12 prn11 prn10 positive polarity register negative polarity register 8 5 6 5 v1 figure 36 . grayscale control
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 78 structure of grayscale amplifier the structure of the grayscale amplifier is shown as below. determine 8 level (vin0-vin7) by the gradient adjuster and the micro adjustment register. also, period of each level is split by the internal ladder resistance and generates level between v0 to v 63. gradient adjustment register micro adjustment register (6 x 3 bits) prp/n0 prp/n1 pkp/n0 pkp/n1 pkp/n2 pkp/n3 pkp/n4 pkp/n5 oscillation adjustment register vrp/vrn 8 to 1 selector vdh 8 to 1 selector 8 to 1 selector 8 to 1 selector 8 to 1 selector vgs ladder resistance grayscale amplifier 8 to 1 selector 3 3 3 3 3 3 3 3 5 vinp0/vinn0 vinp1/vinn1 vinp2/vinn2 vinp3/vinn3 vinp4/vinn4 vinp5/vinn5 vinp6/vinn6 vinp7/vinn7 v0 v1 v2 v3 v8 v9 v20 v21 v43 v44 v55 v56 v57 v62 v63 figure 37 . structure of grayscale amplifier
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 79 8 to1 sel 8 to1 sel 8 to1 sel 8 to1 sel 8 to1 sel 8 to1 sel kvp1 kvp2 kvp3 kvp4 kvp5 kvp6 kvp7 kvp8 kvp9 kvp10 kvp11 kvp12 kvp13 kvp14 kvp15 kvp16 kvp17 kvp18 kvp19 kvp20 kvp21 kvp22 kvp23 kvp24 kvp25 kvp26 kvp27 kvp28 kvp29 kvp30 kvp31 kvp32 kvp33 kvp34 kvp35 kvp36 kvp37 kvp38 kvp39 kvp40 kvp41 kvp42 kvp43 kvp44 kvp45 kvp46 kvp47 kvp48 v v v v v v vinp0 vinp1 vinp2 vinp3 vinp4 vinp5 vinp6 vinp7 kvp49 kvp0 pkp0[2:0] pkp1[2:0] pkp2[2:0] pkp3[2:0] pkp4[2:0] pkp5[2:0] prp0[2:0] prp1[2:0] vrp[2:0] 5 r 4 r 1 r 1 r 1 r 1 r 4 r 5 r 8 r vrp 0 to 31r vrlp 0 to 28r 5 r 16 r 5 r vrhp 0 to 28r rp0 rp1 rp2 rp3 rp4 rp5 rp6 rp7 rp8 rp9 rp10 rp11 rp12 rp13 rp14 rp15 rp16 rp17 rp18 rp19 rp20 rp21 rp22 rp23 rp24 rp25 rp26 rp27 rp28 rp29 rp30 rp31 rp32 rp33 rp34 rp35 rp36 rp37 rp38 rp39 rp40 rp41 rp42 rp43 rp44 rp45 rp46 rp47 8 to1 sel 8 to1 sel 8 to1 sel 8 to1 sel 8 to1 sel 8 to1 sel kvn1 kvn2 kvn3 kvn4 kvn5 kvn6 kvn7 kvn8 kvn9 kvn10 kvn11 kvn12 kvn13 kvn14 kvn15 kvn16 kvn17 kvn18 kvn19 kvn20 kvn21 kvn22 kvn23 kvn24 kvn25 kvn26 kvn27 kvn28 kvn29 kvn30 kvn31 kvn32 kvn33 kvn34 kvn35 kvn36 kvn37 kvn38 kvn39 kvn40 kvn41 kvn42 kvn43 kvn44 kvn45 kvn46 kvn47 kvn48 v v v v v v vinn0 vinn1 vinn2 vinn3 vinn4 vinn5 vinn6 vinn7 kvn49 kvn0 pkn0[2:0] pkn1[2:0] pkn2[2:0] pkn3[2:0] pkn4[2:0] pkn5[2:0] prn0[2:0] prn1[2:0] vrn[2:0] 5 r 4 r 1 r 1 r 1 r 1 r 4 r 5 r 8 r vrn 0 to 31r vrln 0 to 28r 5 r 16 r 5 r vrhn 0 to 28r rn0 rn1 rn2 rn3 rn4 rn5 rn6 rn7 rn8 rn9 rn10 rn11 rn12 rn13 rn14 rn15 rn16 rn17 rn18 rn19 rn20 rn21 rn22 rn23 rn24 rn25 rn26 rn27 rn28 rn29 rn30 rn31 rn32 rn33 rn34 rn35 rn36 rn37 rn38 rn39 rn40 rn41 rn42 rn43 rn44 rn45 rn46 rn47 exvr ( ) vdh figure 38 . structure of ladder/8 to 1 selector
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 80 gamma adjustment register this block is the register to set up the grayscale voltage adjusting to the gamma specification of the lcd panel. this register can independent set up to positive/negative polarities and there are 3 types of register groups to adjust gradient and oscillation on number of the grayscale, characteristics of the grayscale voltage. (but, r.g.b. is commonness.) following graphics indicates the operation of each adjusting register. grayscale number grayscale voltage a) gradient adjustment grayscale number grayscale voltage grayscale number grayscale voltage b) oscillation adjustment c) micro-adjustment figure 39 . the operation of adjusting register gradient adjusting resistor the gradient adjusting resistor is to adjust around middle gradient, specification of the grayscale number and the grayscale voltage without changing the dynamic range. to accomplish the adjustment, it controls the variable resistor (vrhp (n) / vrl (n)) of the ladder resistor for the grayscale voltage generator. also, there is an independent resistor on the positive/negative polarities in order for corresponding to asymmetry drive. oscillation adjusting resistor the oscillation-adjusting resistor is to adjust oscillation of the grayscale voltage. to accomplish the adjustment, it controls the variable resistor (vrp (n)) of the ladder resistor for the grayscale voltage generator located at lower side of the ladder resistor. (adjust upper side by input gvdd level.) also, there is an independent resistor on the positive/negative polarities as well as the gradient adjusting resistor. micro-adjusting resistor the micro-adjusting resistor is to make subtle adjustment of the grayscale voltage level. to accomplish the adjustment, it controls the each reference voltage level by the 8 to 1 selector towards the 8-leveled reference voltage generated from the ladder resistor. also, there is an independent resistor on the positive/negative polarities as well as other adjusting resistors.
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 81 table 30 . gamma adjusting register register positive polarity negative polarity set-up contents prp0[2:0] prn0[2:0] variable resistor vrhp(n) gradient adjustment prp1[2:0] prn1[2:0] variable resistor vrlp(n) oscillation adjustment vrp[4:0] vrn[4:0] variable resistor vrp(n) pkp0[2:0] pkn0[2:0] the voltage of grayscale number 1 is selected by the 8 to 1 selector pkp1[2:0] pkn1[2:0] the voltage of grayscale number 8 is selected by the 8 to 1 selector pkp3[2:0] pkn3[2:0] the voltage of grayscale number 20 is selected by the 8 to 1 selector pkp4[2:0] pkn4[2:0] the voltage of grayscale number 43 is selected by the 8 to 1 selector pkp5[2:0] pkn5[2:0] the voltage of grayscale number 55 is selected by the 8 to 1 selector micro-adjustment pkp6[2:0] pkn6[2:0] the voltage of grayscale number 62 is selected by the 8 to 1 selector
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 82 ladder resistor/8 to 1 selector this block outputs the reference voltage of the grayscale voltage. there are two ladder resistors including the variable resistor and the 8 to 1 selector selecting voltage generated by the ladder resistance voltage. the variable and 8 to 1 resistors are controlled by the gamma resistor. also, there are pins that connect to the external volume resistor. and it allows to compensate the dispersion of length between one panel to another. variable resistor there are 2 types of the variable resistors that is for the gradient adjustment (vrhp (n) / vrlp (n)) and for the oscillation adjustment (vrp (n)). the resistance value is set by the gradient adjusting resistor and the oscillation adjusting resistor as below. table 31 . gradient adjustment register value prp(n) [2:0 ] resistance value prp(n) 000 0r 001 4r 010 8r 011 12r 100 16r 101 20r 110 24r 111 28r table 32 . oscillation adjustment register value vrp(n) [2:0 ] resistance value vrp(n) 00000 0r 00001 1r 00010 2r . . . . . . 11101 29r 11110 30r 11111 31r
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 83 the 8 to 1 selector in the 8 to 1 selector, the voltage level must be selected given by the ladder resistance and the micro-adjusting register. and output the voltage the six types of the reference voltage, the vin1- to vin6. following figure explains the relationship between the micro-adjusting register and the selecting voltage. table 33 . relationship between micro-adjusting register and selected voltage selected voltage register value pkp(n) [2 : 0] vinp(n)1 vinp(n)2 vinp(n)3 vinp(n)4 vinp(n)5 vinp(n)6 000 kvp(n)1 kvp(n)9 kvp(n)17 kvp(n)25 kvp(n)33 kvp(n)41 001 kvp(n)2 kvp(n)10 kvp(n)18 kvp(n)26 kvp(n)34 kvp(n)42 010 kvp(n)3 kvp(n)11 kvp(n)19 kvp(n)27 kvp(n)35 kvp(n)43 011 kvp(n)4 kvp(n)12 kvp(n)20 kvp(n)28 kvp(n)36 kvp(n)44 100 kvp(n)5 kvp(n)13 kvp(n)21 kvp(n)29 kvp(n)37 kvp(n)45 101 kvp(n)6 kvp(n)14 kvp(n)22 kvp(n)30 kvp(n)38 kvp(n)46 110 kvp(n)7 kvp(n)15 kvp(n)23 kvp(n)31 kvp(n)39 kvp(n)47 111 kvp(n)8 kvp(n)16 kvp(n)24 kvp(n)32 kvp(n)40 kvp(n)48
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 84 table 34 . gamma adjusting voltage formula (positive polarity) pins formula micro-adjusting register value reference voltage kvp0 gvdd - vinp0 kvp1 gvdd- d v *5r/sumrp pkp02-00 = ? 000 ? kvp2 gvdd- d v *9r/sumrp pkp02-00 = ? 001 ? kvp3 gvdd- d v *13r/sumrp pkp02-00 = ? 010 ? kvp4 gvdd- d v *17r/sumrp pkp02-00 = ? 011 ? kvp5 gvdd- d v *21r/sumrp pkp02-00 = ? 100 ? kvp6 gvdd- d v *25r/sumrp pkp02-00 = ? 101 ? kvp7 gvdd- d v *29r/sumrp pkp02-00 = ? 110 ? kvp8 gvdd- d v *33r/sumrp pkp02-00 = ? 111 ? vinp1 kvp9 gvdd- d v * ( 33r +vrhp) /sumrp pkp12-10 = ? 000 ? kvp10 gvdd- d v * ( 34r +vrhp) /sumrp pkp12-10 = ? 001 ? kvp11 gvdd- d v * ( 35r +vrhp) /sumrp pkp12-10 = ? 010 ? kvp12 gvdd- d v * ( 36r +vrhp) /sumrp pkp12-10 = ? 011 ? kvp13 gvdd- d v * ( 37r +vrhp) /sumrp pkp12-10 = ? 100 ? kvp14 gvdd- d v * ( 38r +vrhp) /sumrp pkp12-10 = ? 101 ? kvp15 gvdd- d v * ( 39r +vrhp) /sumrp pkp12-10 = ? 110 ? kvp16 gvdd- d v * ( 40r +vrhp) /sumrp pkp12-10 = ? 111 ? vinp2 kvp17 gvdd- d v * ( 45r +vrhp) /sumrp pkp22-20 = ? 000 ? kvp18 gvdd- d v * ( 46r +vrhp) /sumrp pkp22-20 = ? 001 ? kvp19 gvdd- d v * ( 47r +vrhp) /sumrp pkp22-20 = ? 010 ? kvp20 gvdd- d v * ( 48r +vrhp) /sumrp pkp22-20 = ? 011 ? kvp21 gvdd- d v * ( 49r +vrhp) /sumrp pkp22-20 = ? 100 ? kvp22 gvdd- d v * ( 50r +vrhp) /sumrp pkp22-20 = ? 101 ? kvp23 gvdd- d v * ( 5 1 r +vrhp) /sumrp pkp22-20 = ? 110 ? kvp24 gvdd- d v * ( 5 2 r +vrhp) /sumrp pkp22-20 = ? 111 ? vinp3 kvp25 gvdd- d v * ( 68r +vrhp) /sumrp pkp32-30 = ? 000 ? kvp26 gvdd- d v * ( 69r +vrhp) /sumrp pkp32-30 = ? 001 ? kvp27 gvdd- d v * ( 70r +vrhp) /sumrp pkp32-30 = ? 010 ? kvp28 gvdd- d v * ( 71r +vrhp) /sumrp pkp32-30 = ? 011 ? kvp29 gvdd- d v * ( 72r +vrhp) /sumrp pkp32-30 = ? 100 ? kvp30 gvdd- d v * ( 73r +vrhp) /sumrp pkp32-30 = ? 101 ? kvp31 gvdd- d v * ( 74r +vrhp) /sumrp pkp32-30 = ? 110 ? kvp32 gvdd- d v * ( 75r +vrhp) /sumrp pkp32-30 = ? 111 ? vinp4 kvp33 gvdd- d v * ( 80r +vrhp) /sumrp pkp42-40 = ? 000 ? kvp34 gvdd- d v * ( 81r +vrhp) /sumrp pkp42-40 = ? 001 ? kvp35 gvdd- d v * ( 82r +vrhp) /sumrp pkp42-40 = ? 010 ? kvp36 gvdd- d v * ( 83r +vrhp) /sumrp pkp42-40 = ? 011 ? kvp37 gvdd- d v * ( 84r +vrhp) /sumrp pkp42-40 = ? 100 ? kvp38 gvdd- d v * ( 85r +vrhp) /sumrp pkp42-40 = ? 101 ? kvp39 gvdd- d v * ( 86r +vrhp) /sumrp pkp42-40 = ? 110 ? kvp40 gvdd- d v * ( 87r +vrhp) /sumrp pkp42-40 = ? 111 ? vinp5 kvp41 gvdd- d v * ( 87r +vrhp+vrlp) /sumrp pkp52-50 = ? 000 ? kvp42 gvdd- d v * ( 91r +vrhp+vrlp) /sumrp pkp52-50 = ? 001 ? kvp43 gvdd- d v * ( 95r +vrhp+vrlp) /sumrp pkp52-50 = ? 010 ? kvp44 gvdd- d v * ( 99r +vrhp+vrlp) /sumrp pkp52-50 = ? 011 ? kvp45 gvdd- d v * ( 103r +vrhp+vrlp) /sumrp pkp52-50 = ? 100 ? kvp46 gvdd- d v * ( 107r +vrhp+vrlp) /sumrp pkp52-50 = ? 101 ? kvp47 gvdd- d v * ( 111r +vrhp+vrlp) /sumrp pkp52-50 = ? 110 ? kvp48 gvdd- d v * ( 115r +vrhp+vrlp) /sumrp pkp52-50 = ? 111 ? vinp6 kvp49 gvdd- d v * ( 120r +vrhp+vrlp) /sumrp - vinp7 sumrp: total of the positive polarity ladder resistance = 128r + vrhp + vrlp + vrp sumrp: total of the negative polarity ladder resistance = 128r + vrhn + vrln + vrn d v: potential difference between kv0 and kv49 = gvdd*sumrp*sumrn / [sumrp*sumrn+exvr*(sumrp+sumrn)]
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 85 table 35 . gamma voltage formula (positive polarity) grayscale voltage formula grayscale voltage formula v0 vinp0 v32 v43+(v20-v43)*(11/23) v1 vinp1 v33 v43+(v20-v43)*(10/23) v2 v3+(v1-v3)*(8/24) v34 v43+(v20-v43)*(9/23) v3 v8+(v1-v8)*(450/800) v35 v43+(v20-v43)*(8/23) v4 v8+(v3-v8)*(16/24) v36 v43+(v20-v43)*(7/23) v5 v8+(v3-v8)*(12/24) v37 v43+(v20-v43)*(6/23) v6 v8+(v3-v8)*(8/24) v38 v43+(v20-v43)*(5/23) v7 v8+(v3-v8)*(4/24) v39 v43+(v20-v43)*(4/23) v8 vinp2 v40 v43+(v20-v43)*(3/23) v9 v20+(v8-v20)*(22/24) v41 v43+(v20-v43)*(2/23) v10 v20+(v8-v20)*(20/24) v42 v43+(v20-v43)*(1/23) v11 v20+(v8-v20)*(18/24) v43 vinp4 v12 v20+(v8-v20)*(16/24) v44 v55+(v43-v55)*(22/24) v13 v20+(v8-v20)*(14/24) v45 v55+(v43-v55)*(20/24) v14 v20+(v8-v20)*(12/24) v46 v55+(v43-v55)*(18/24) v15 v20+(v8-v20)*(10/24) v47 v55+(v43-v55)*(16/24) v16 v20+(v8-v20)*(8/24) v48 v55+(v43-v55)*(14/24) v17 v20+(v8-v20)*(6/24) v49 v55+(v43-v55)*(12/24) v18 v20+(v8-v20)*(4/24) v50 v55+(v43-v55)*(10/24) v19 v20+(v8-v20)*(2/24) v51 v55+(v43-v55)*(8/24) v20 vinp3 v52 v55+(v43-v55)*(6/24) v21 v43+(v20-v43)*(22/23) v53 v55+(v43-v55)*(4/24) v22 v43+(v20-v43)*(21/23) v54 v55+(v43-v55)*(2/24) v23 v43+(v20-v43)*(20/23) v55 vinp5 v24 v43+(v20-v43)*(19/23) v56 v60+(v55-v60)*(20/24) v25 v43+(v20-v43)*(18/23) v57 v60+(v55-v60)*(16/24) v26 v43+(v20-v43)*(17/23) v58 v60+(v55-v60)*(12/24) v27 v43+(v20-v43)*(16/23) v59 v60+(v55-v60)*(8/24) v28 v43+(v20-v43)*(15/23) v60 v62+(v55-v62)*(350/800) v29 v43+(v20-v43)*(14/23) v61 v62+(v60-v62)*(16/24) v30 v43+(v20-v43)*(13/23) v62 vinp6 v31 v43+(v20-v43)*(12/23) v63 vinp7
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 86 table 36 . gamma adjusting voltage formula (negative polarity) pins formula micro-adjusting register value reference voltage kvn0 gvdd - vinn0 kvn1 gvdd- d v *5r/sumrn pkn02-00 = ? 000 ? kvn2 gvdd- d v *9r/sumrn pkn02-00 = ? 001 ? kvn3 gvdd- d v *13r/sumrn pkn02-00 = ? 010 ? kvn4 gvdd- d v *17r/sumrn pkn02-00 = ? 011 ? kvn5 gvdd- d v *21r/sumrn pkn02-00 = ? 100 ? kvn6 gvdd- d v *25r/sumrn pkn02-00 = ? 101 ? kvn7 gvdd- d v *29r/sumrn pkn02-00 = ? 110 ? kvn8 gvdd- d v *33r/sumrn pkn02-00 = ? 111 ? vinn1 kvn9 gvdd- d v * ( 33r +vrhn) /sumrn pkn12-10 = ? 000 ? kvn10 gvdd- d v * ( 34r +vrhn) /sumrn pkn12-10 = ? 001 ? kvn11 gvdd- d v * ( 35r +vrhn) /sumrn pkn12-10 = ? 010 ? kvn12 gvdd- d v * ( 36r +vrhn) /sumrn pkn12-10 = ? 011 ? kvn13 gvdd- d v * ( 37r +vrhn) /sumrn pkn12-10 = ? 100 ? kvn14 gvdd- d v * ( 38r +vrhn) /sumrn pkn12-10 = ? 101 ? kvn15 gvdd- d v * ( 39r +vrhn) /sumrn pkn12-10 = ? 110 ? kvn16 gvdd- d v * ( 40r +vrhn) /sumrn pkn12-10 = ? 111 ? vinn2 kvn17 gvdd- d v * ( 45r +vrhn) /sumrn pkn22-20 = ? 000 ? kvn18 gvdd- d v * ( 46r +vrhn) /sumrn pkn22-20 = ? 001 ? kvn19 gvdd- d v * ( 47r +vrhn) /sumrn pkn22-20 = ? 010 ? kvn20 gvdd- d v * ( 48r +vrhn) /sumrn pkn22-20 = ? 011 ? kvn21 gvdd- d v * ( 49r +vrhn) /sumrn pkn22-20 = ? 100 ? kvn22 gvdd- d v * ( 50r +vrhn) /sumrn pkn22-20 = ? 101 ? kvn23 gvdd- d v * ( 5 1 r +vrhn) /sumrn pkn22-20 = ? 110 ? kvn24 gvdd- d v * ( 5 2 r +vrhn) /sumrn pkn22-20 = ? 111 ? vinn3 kvn25 gvdd- d v * ( 68r +vrhn) /sumrn pkn32-30 = ? 000 ? kvn26 gvdd- d v * ( 69r +vrhn) /sumrn pkn32-30 = ? 001 ? kvn27 gvdd- d v * ( 70r +vrhn) /sumrn pkn32-30 = ? 010 ? kvn28 gvdd- d v * ( 71r +vrhn) /sumrn pkn32-30 = ? 011 ? kvn29 gvdd- d v * ( 72r +vrhn) /sumrn pkn32-30 = ? 100 ? kvn30 gvdd- d v * ( 73r +vrhn) /sumrn pkn32-30 = ? 101 ? kvn31 gvdd- d v * ( 74r +vrhn) /sumrn pkn32-30 = ? 110 ? kvn32 gvdd- d v * ( 75r +vrhn) /sumrn pkn32-30 = ? 111 ? vinn4 kvn33 gvdd- d v * ( 80r +vrhn) /sumrn pkn42-40 = ? 000 ? kvn34 gvdd- d v * ( 81r +vrhn) /sumrn pkn42-40 = ? 001 ? kvn35 gvdd- d v * ( 82r +vrhn) /sumrn pkn42-40 = ? 010 ? kvn36 gvdd- d v * ( 83r +vrhn) /sumrn pkn42-40 = ? 011 ? kvn37 gvdd- d v * ( 84r +vrhn) /sumrn pkn42-40 = ? 100 ? kvn38 gvdd- d v * ( 85r +vrhn) /sumrn pkn42-40 = ? 101 ? kvn39 gvdd- d v * ( 86r +vrhn) /sumrn pkn42-40 = ? 110 ? kvn40 gvdd- d v * ( 87r +vrhn) /sumrn pkn42-40 = ? 111 ? vinn5 kvn41 gvdd- d v * ( 87r +vrhn+vrln) /sumrn pkn52-50 = ? 000 ? kvn42 gvdd- d v * ( 91r +vrhn+vrln) /sumrn pkn52-50 = ? 001 ? kvn43 gvdd- d v * ( 95r +vrhn+vrln) /sumrn pkn52-50 = ? 010 ? kvn44 gvdd- d v * ( 99r +vrhn+vrln) /sumrn pkn52-50 = ? 011 ? kvn45 gvdd- d v * ( 103r +vrhn+vrln) /sumrn pkn52-50 = ? 100 ? kvn46 gvdd- d v * ( 107r +vrhn+vrln) /sumrn pkn52-50 = ? 101 ? kvn47 gvdd- d v * ( 111r +vrhn+vrln) /sumrn pkn52-50 = ? 110 ? kvn48 gvdd- d v * ( 115r +vrhn+vrln) /sumrn pkn52-50 = ? 111 ? vinn6 kvn49 gvdd- d v * ( 120r +vrhn+vrln) /sumrn - vinn7 sumrp: total of the positive polarity ladder resistance = 128r + vrhp + vrlp + vrp sumrn: total of the negative polarity ladder resistance = 128r + vrhn + vrln + vrn d v: potential difference between kv0 and kv49 = gvdd*sumrp*sumrn / [sumrp*sumrn+exvr*(sumrp+sumrn)]
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 87 table 37 . gamma voltage formula (negative polarity) grayscale voltage formula grayscale voltage formula v0 vinn0 v32 v43+(v20-v43)*(11/23) v1 vinn1 v33 v43+(v20-v43)*(10/23) v2 v3+(v1-v3)*(8/24) v34 v43+(v20-v43)*(9/23) v3 v8+(v1-v8)*(450/800) v35 v43+(v20-v43)*(8/23) v4 v8+(v3-v8)*(16/24) v36 v43+(v20-v43)*(7/23) v5 v8+(v3-v8)*(12/24) v37 v43+(v20-v43)*(6/23) v6 v8+(v3-v8)*(8/24) v38 v43+(v20-v43)*(5/23) v7 v8+(v3-v8)*(4/24) v39 v43+(v20-v43)*(4/23) v8 vinn2 v40 v43+(v20-v43)*(3/23) v9 v20+(v8-v20)*(22/24) v41 v43+(v20-v43)*(2/23) v10 v20+(v8-v20)*(20/24) v42 v43+(v20-v43)*(1/23) v11 v20+(v8-v20)*(18/24) v43 vinn4 v12 v20+(v8-v20)*(16/24) v44 v55+(v43-v55)*(22/24) v13 v20+(v8-v20)*(14/24) v45 v55+(v43-v55)*(20/24) v14 v20+(v8-v20)*(12/24) v46 v55+(v43-v55)*(18/24) v15 v20+(v8-v20)*(10/24) v47 v55+(v43-v55)*(16/24) v16 v20+(v8-v20)*(8/24) v48 v55+(v43-v55)*(14/24) v17 v20+(v8-v20)*(6/24) v49 v55+(v43-v55)*(12/24) v18 v20+(v8-v20)*(4/24) v50 v55+(v43-v55)*(10/24) v19 v20+(v8-v20)*(2/24) v51 v55+(v43-v55)*(8/24) v20 vinn3 v52 v55+(v43-v55)*(6/24) v21 v43+(v20-v43)*(22/23) v53 v55+(v43-v55)*(4/24) v22 v43+(v20-v43)*(21/23) v54 v55+(v43-v55)*(2/24) v23 v43+(v20-v43)*(20/23) v55 vinn5 v24 v43+(v20-v43)*(19/23) v56 v60+(v55-v60)*(20/24) v25 v43+(v20-v43)*(18/23) v57 v60+(v55-v60)*(16/24) v26 v43+(v20-v43)*(17/23) v58 v60+(v55-v60)*(12/24) v27 v43+(v20-v43)*(16/23) v59 v60+(v55-v60)*(8/24) v28 v43+(v20-v43)*(15/23) v60 v62+(v55-v62)*(350/800) v29 v43+(v20-v43)*(14/23) v61 v62+(v60-v62)*(16/24) v30 v43+(v20-v43)*(13/23) v62 vinn6 v31 v43+(v20-v43)*(12/23) v63 vinn7
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 88 positive polarity negative polarity v0 v63 output level ram data db15-11, 4-0: 00000 db10-5: 000000 db15-11, 4-0: 11111 db10-5: 111111 figure 40 . relationship between ram data and output voltage positive polarity negative polarity sn vcom figure 41 . relationship between source output and vcom
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 89 the 8-color display mode the S6D0110 carries 8-color display mode. using grayscale levels are v0 and v63 and all other level power supplies are halt. so that it attempts to lower power consumption. also, during the 8-color mode, the gamma micro adjustment register, pkp00-pkp52 and pkn00-pkn52 are invalid. rewrite the data of gram r/b to 00000 or 11111, g to 000000 or 111111 before set the mode. the level power supply (v1-v62) is in off condition during the 8-color mode in order to select v0/v63. r04 r03 r02 r01 r00 g05 g04 g03 g02 g01 g00 b04 b03 b02 b01 b00 graphics ram (gram) msb lsb on/off control on/off control on/off control lcd driver lcd driver lcd driver r g b lcd grayscale amplifier 2 v0 v63 pkp02 pkp01 pkp00 pkp12 pkp11 pkp10 pkp22 pkp21 pkp20 pkp32 pkp31 pkp30 pkp42 pkp41 pkp40 pkp52 pkp51 pkp50 prp02 prp01 prp00 prp12 prp11 prp10 pkn02 pkn01 pkn00 pkn12 pkn11 pkn10 pkn22 pkn21 pkn20 pkn32 pkn31 pkn30 pkn42 pkn41 pkn40 pkn52 pkn51 pkn50 prn02 prn01 prn00 prn12 prn11 prn10 positive polarity register negative polarity register 8 5 6 5 figure 42 . 8-color display control
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 90 off gon= ? 1 ? dte= ? 1 ? d1-0= ? 10 ? wait (2 frame or higher) on gon= ? 1 ? dte= ? 0 ? d1-0= ? 10 ? off gon= ? 0 ? dte= ? 0 ? d1-0= ? 00 ? wait (2 frame or higher) ram setup cl= ? 1 ? wait (40ms or higher) on gon= ? 0 ? dte= ? 0 ? d1-0= ? 01 ? wait (2 frame or higher) on gon= ? 1 ? dte= ? 0 ? d1-0= ? 01 ? on gon= ? 1 ? dte= ? 0 ? d1-0= ? 11 ? on gon= ? 1 ? dte= ? 1 ? d1-0= ? 11 ? display by 8-color mode off gon= ? 1 ? dte= ? 1 ? d1-0= ? 10 ? wait (2 frame or higher) on gon= ? 1 ? dte= ? 0 ? d1-0= ? 10 ? off gon= ? 0 ? dte= ? 0 ? d1-0= ? 00 ? wait (2 frame or higher) ram setup cl= ? 0 ? wait (40ms or higher) on gon= ? 0 ? dte= ? 0 ? d1-0= ? 01 ? wait (2 frame or higher) on gon= ? 1 ? dte= ? 0 ? d1-0= ? 01 ? on gon= ? 1 ? dte= ? 0 ? d1-0= ? 11 ? on gon= ? 1 ? dte= ? 1 ? d1-0= ? 11 ? display by 65,536-color mode wait (2 frame or higher) wait (2 frame or higher) <65,536- color => 8-color> <8- color => 65,536 -color> figure 43 . set up procedure for the 8-color mode
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 91 system structure example following diagram indicates the system structure, which composes the 132 (width) x 176 (length) dots tft-lcd panel. 132rgb x 176 dot tft lcd panel S6D0110 csb rs e r/w db[15:0] im[2:0] resetb s1 s2 s3 s394 s395 s396 csb rs e r/w db[15:0] im[2:0] resetb g2 g4 g176 g174 g1 g3 g175 g173 figure 44 . system structure
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 92 instruction set up flow display off gon= 1 dte= 1 d1-0= 10 wait (more than 2 frames) display off gon= 1 dte= 0 d1-0= 10 wait (more than 2 frames) display off gon= 0 dte= 0 d1-0= 00 display off power off sap2-0= 000 ap2-0= 000 continue to the display on flow power setting display on gon= 0 dte= 0 d1-0= 01 wait (more than 2 frames) display on gon= 1 dte= 0 d1-0= 01 display on gon= 1 dte= 0 d1-0= 11 display on gon= 1 dte= 1 d1-0= 11 display on continue to the display on flow < display off> < display on> eq=0 wait (more than 2 frames) figure 45 . instruction set up flow
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 93 < standby> < sleep> display off flow standby set (stb= 1 ) oscillation start wait 10ms standby cancel (stb= 0 ) power setting display on flow display off flow sleep set (slp= 1 ) sleep cancel (slp= 0 ) power setting display on flow standby set standby cancel sleep set sleep cancel figure 46 . instruction setup flow (continued)
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 94 oscillation circuit the S6D0110 can oscillate between the osc1 and osc2 pins using an internal r-c oscillator with an external oscillation resistor. note that in r-c oscillation, the oscillation frequency is changed according to the external resistance value, wiring length, or operating power-supply voltage. if rf is increased or power supply voltage is decrease, the oscillation frequency decreases. for the relationship between rf resistor value and oscillation frequency, see the electric characteristics notes section. osc1 osc2 S6D0110 clock (200 khz) damping resistance (2 k w ) 1) external clock mode 2) external resistance oscillation mode osc1 osc2 S6D0110 rf note: the rf resistance must be located near the osc1/osc2 pin on the chip figure 47 . oscillation circuit
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 95 n-raster-row reversed ac drive the S6D0110 supports not only the lcd reversed ac drive in a one-frame unit but also the n-raster-row reversed ac drive which alternates in an n-raster-row unit from one to 64 raster-rows. when a problem affecting display quality occurs, the n-raster-row reversed ac drive can improve the quality. determine the number of the raster-rows n (nw bit set value +1) for alternating after confirmation of the display quality with the actual lcd panel. however, if the number of ac raster-row is reduced, the lcd alternating frequency becomes high. because of this, the charge or discharge current is increased in the lcd cells. 1 2 3 4 175 176 184 1 2 3 4 175 176 184 1 2 1 frame 1 frame blank period blank period frame a/c waveform drive 176 raster-row n-raster-row a/c waveform drive 176 raster-row reverse 3 raster-row eor= ? 1 ? figure 48 . example of an ac signal under n-raster-row reversed ac drive
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 96 interlace drive S6D0110 supports the interlace drive to protect from the flicker. it splits one frame into n fields and drives. determine the n fields (fld bit stetting value) after confirming on the actual lcd display. following table indicates n fields: the gate selecting position when it is 1 or 3. a nd the diagram below indicates the output waveform when the field interlace drive is active. gs= ? 0 ? fld1-0 setting value 01 11 field gate - (1) (2) (3) g1 o o g2 o o g3 o o g4 o o g5 o o g6 o o g7 o o g8 o o g9 o o ? ? g173 o o g174 o o g175 o o g176 o o gs= ? 1 ? fld1-0 setting value 01 11 field gate - (1) (2) (3) g176 o o g175 o o g174 o o g173 o o g172 o o g171 o o g170 o o g169 o o g168 o o ? ? g4 o o g3 o o g2 o o g1 o o 1 frame blank period field (1) field (2) field (3) field (1) ac polarity g1 g2 g3 g4 g5 g6 g3n+1 g3n+2 g3n+3 figure 49 . interlace drive and output waveform
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 97 a/c timing following diagram indicates the a/c timing on the each a/c drive method. after every 1 drawing, the a/c timing is occurred on the reversed frame ac drive. after the a/c timing, the blank (all gate output : vgoff level ) period described below is inserted. w hen it is on the interlace drive , blank period is inserted every a/c timing. when the reversed n-raster-row is driving, a blank period is inserted after all screens are drawn. front and back porch can be adjusted using fp3-0 and bp3-0 bits (r08h). in interlace drive mode, blank period can be adjusted using blp13- 0 and blp23-0 bit (r09h). blank period = back porch + blank period 1 + blank period 2 + front porch frame 1 frame reverse ac drive 1 frame period field 1 a/c a/c a/c blank period = back porch + front porch 3 field interlace drive n-raster-row reversed ac drive front porch back porch a/c timing 1 frame period front porch field 2 field 3 blank period 2 (blp2) blank period 1 (blp1) back porch a/c 1 frame period front porch back porch a/c a/c a/c a/c a/c a/c a/c a/c a/c a/c n-raster-row blank period = back porch + front porch n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row figure 50 . a/c timing
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 98 frame frequency adjusting function the S6D0110 has an on-chip frame-frequency adjustment function. the frame frequency can be adjusted by the instruction setting (div, rtn) during the lcd driver as the oscillation frequency is always same. if the oscillation frequency is set to high, animation or a static image can be displayed in suitable ways by changing the frame frequency. when a static image is displayed, the frame frequency can be set low and the low-power consumption mode can be entered. when high-speed screen switching for an animated display, etc. is required, the frame frequency can be set high. relationship between lcd drive duty and frame frequency the relationships between the lcd drive duty and the frame frequency is calculated by the following expression. the frame frequency can be adjusted in the 1h period adjusting bit (rtn) and in the operation clock division bit (div) by the instruction. frame frequency = f osc clock cycles per raster-row x division ratio x (line+b) [ hz] f osc : r-c oscillation frequency line: number of raster-rows (nl bit) clock cycles per raster-row: rtn bit division ratio: div bit b: blank period(back porch + front porch) figure 51 . formula for the frame frequency example calculation driver raster-row : 176 1h period: 16 clock (rtn3 to 0 = 0000) operation clock division ratio: 1division b: blank period (bp + fp): 8 fosc = 60hz x (0+16) clock x 1 division x (176+ b ) lines = 177 [khz] in this case, the r c oscillation frequency becomes 177 khz. the external resistance value of the rc oscillator must be adjusted to be 177 khz. note: when fld1-0= ? 11 ? (interlace drive), b = bp + fp + blp1 + blp2
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 99 screen-division driving function the S6D0110 can select and drive two screens at any position with the screen-driving position registers (r14 and r15). any two screens required for display are selectively driven and reducing lcd-driving voltage and power consumption. for the 1 st division screen, start line (ss17 to 10) and end line (se17 to 10) are specified by the 1 st screen-driving position register (r14). for the 2 nd division screen, start line (ss27 to 20) and end line (se27 to 20) are specified by the 2 nd screen-driving position register (r15). the 2 nd screen control is effective when the spt bit is 1. the total count of selection-driving lines for the 1 st and 2 nd screens must correspond to the lcd-driving duty set value. rm * oct 14th 10:18am g1 g7 g26 g42 1 st screen: 7-raster-row driving non-display area 2nd screen: 17 raster-row driving non-display area driving raster-row: nl4-0 = 10101 (176 lines) 1st screen setting: ss17-10 = 00h, se17-10 = 06h 2nd screen setting: ss27-20 = 19h, se27-20 = 29h, spt = 1 figure 52 . driving on 2 screen
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 100 restriction on the 1 st /2 nd screen driving position register settings the following restrictions must be satisfied when setting the start line (ss17 to 10) and end line (se17 to 10) of the 1 st screen driving position register (r14) and the start line (ss27 to 20) and end line (se27 to 20) of the 2 nd screen driving position register (r15) for the S6D0110. note that incorrect display may occur if the restrictions are not satisfied. table 38 . restrictions on the 1 st /2 nd screen driving position register setting 1 st screen driving (spt=0) register setting display operation (se17 to 10) ? (ss17 to 10) = nl full screen display normally displays (se17 to 10) to (ss17 to 10) (se17 to 10) ? (ss17 to 10) < nl partial display normally displays (se17 to 10) to (ss17 to 10) white display for all other times (ram data is not related at all) (se17 to 10) ? (ss17 to 10) > nl setting disabled note 1: ss17 to 10 se17 to 10 afh note 2: setting se27 to 20 and ss27 to 20 are invalid 2 nd screen driving (spt=1) register setting display operation ((se17 to 10) ? (ss17 to 10)) + ((se27 to 20) ? (ss27-20)) = nl full screen display normally displays (se27 to 10) to (ss17 to 10) ((se17 to 10) ? (ss17 to 10)) + ((se27 to 20) ? (ss27-20)) < nl partial display normally displays (se27 to 10) to (ss17 to 10) white display for all other times (ram data is not related at all) ((se17 to 10) ? (ss17 to 10)) + ((se27 to 20) ? (ss27-20)) > nl setting disabled note 1: ss17 to 10 se17 to 10 < ss27 to 20 se27 to 20 afh note 2: (se27 to 20) ? (ss17 to 10) nl the driver output can ? t be set for non-display area during the partial display. determine based on specification of the panels. source output in non-display area pt1 pt0 positive polarity negative polarity gate output in non-display area 0 0 v63 v0 normal drive 0 1 v63 v0 vgoff 1 0 vss vss vgoff 1 1 hi-z hi-z vgoff
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 101 refer to the following flow to set up the partial display. full screen display pt1-0 = 00 set ss/se bits wait (more than 2 frames) pt1-0 = 01 or pt1-0 = 10 or pt1-0 = 11 partial display on set ss/se bits full screen display set as need setting flow for full screen driver split screen drive set up flow figure 53 . partial display set up flow
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 102 application circuit the following figure indicates a schematic diagram of application circuit for S6D0110. S6D0110 vcoml vcomh vcl vci1 vcomr regp regn vci2 avdd gvdd g1 g3 g5 g173 g175 s1 s2 s3 s4 g0 s393 s394 s395 s396 g177 g176 g174 s392 s391 s390 s389 g2 g4 vci4 vbs vci vgoff vgoffout vgoffh vgoffl c11- c11+ c12- c12+ c21+ c21- c22+ c22- c23+ c23- c41+ c41- c31+ c31- vreg2out vreg2 resetb2 db15~8 db7~2 db1/sdo db0/sdi vsso vsso rd wr/scl rs cs vsso vsso contact1 contact2 resetb1 vdd3o im0/id vsso im1 vdd3o im2 vdd3o resetb3 cl1 m flm eq disptmg test vreg1out vreg1 osc1 rf = 100k vcomout pregb vdd3o vsso vgs rdvdd vdd vdd3 vss space only space only *note 3) notes) 1) all capacitor value : 1uf 2) every pins descripted in this diagram have to be wired out externally. 3) "space only" means only space that can arrange curcuit component on it must be ensured. (only "space" is needed to arrange the described circuit component on it.) 4) vsso & vss pin have to be connected externally ( refer to the following figure ) 5) vdd3o & vdd3 pin have to be connected externally ( refer to the following figure ) space only connect externally vsso vss vss vss vss vss internally connected no.91 no.96 connect externally vdd3o vdd3 vdd3 vdd3 vdd3 internally connected no.97 no.100 avss vgh vgl cgnd vci3 external power external power space only osc2 r = 2k signal in * note 3) * note 3) figure 54 . application circuit
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 103 specifications absolute maximum ratings table 39 . absolute maximum rating (vss = 0v) item symbol rating unit supply voltage vdd - 0.3 ~ + 5.0 v supply voltage for step-up circuit vci - 0.3 ~ + 5.0 v lcd supply voltage range |vgh ? vgl| 30 v input v oltage range v in - 0.3 to vdd +0. 5 v operating temperature t opr -40 ~ +85 c storage temperature t stg -55 ~ +110 c notes: 1. absolute maximum rating is the limit value beyond which the ic may be broken. they do not assure operations. 2. operat ing temperature is the range of device-operating temperature. they do not guarantee chip performance. 3. absolute maximum rating is guaranteed when our company ? s package used.
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 104 dc characteristics table 40 . dc characteristics (vss = 0v) characteristic symbol condition min typ max unit note vdd 1.8 - 2.5 v *1 operating voltage vdd 3 2.3 - 3.3 v *1 vgh +7 - 20.0 v vgl -7 - -15.0 v vgoff -5 - -15 v avdd 3.5 5.5 v lcd driving voltage gvdd 3.0 5.0 v input high voltage v ih 0.7vdd3 - vdd3 v *2 input low voltage v il 0 - 0.3vdd3 v *2 output high voltage v oh i oh = -2.0ma vdd3-0.5 vdd3 v *3 output low voltage v ol i ol = 2.0ma 0.0 - 0.5 v *3 input leakage current i il vin = vss or vdd3 -1.0 - 1.0 m a *2 output leakage current i ol vin = vss or vdd3 -3.0 - 3.0 m a *3 operating frequency fosc frame freq. = 60 hz display line = 176 159 177 194 khz *4 internal reference power supply voltage vci 2.5 - 3.3 v 1 st step-up input voltage vci1 1.7 - 2.75 v 1 st step-up output efficiency avdd i load = tbd ma 95 99 - % 2 nd step-up input voltage vci2 3.4 5.5 v 2 nd step-up output efficiency vgh i load = tbd ma 95 99 - % 3 rd step-up input voltage vci3 6.8 15 v 3 rd step-up output efficiency vgl i load = tbd ma 95 99 - % 4 th step-up input voltage vci4 2.5 3.3 v 4 th step-up output efficiency vcl i load = tbd ma 95 99 - % notes : 1. vss = 0v. 2. applied pins; im2-1, csb, e, r/w, rs, db0 to db15, pregb, resetb1,2,3. 3. applied pins; db0 to db15, cl1, m, flm, eq, disptmg. 4. target frame frequency = 60 hz, display line = 176, back porch = 3, front port = 5 internal rtn[3:0] register = ? 0000 ? , internal div[1:0] register = ? 00 ?
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 105 table 41 . dc characteristics for lcd driver outputs (vdd = 1.8v, vdd3 = 3.0v, vss = 0v) characteristic symbol condition min typ max unit note lcd gate driver output on resistance ron vgh ? vgoff=30.0v, vgh=18v, vgoff=-12v, vgo = vgh ? 0.5v - - 2 k *5 lcd source driver high- level output current (gradation output) i hog vso = 4.5v, vsx = 3.5v - - -50 a *6 lcd source driver low- level output current (gradation output) i log vso = 0.5v, vsx = 1.5v 50 - - a *6 4.2v vso - 20 30 mv *6 0.8v < vso < 4.2v - 10 20 mv *6 output voltage deviation (mean value) d vo vso 0.8v - 20 30 mv *6 lcd source driver output voltage range vso - gvdd+0.1 - gvdd-0.1 v lcd source driver high- level output current (binary output) i hob vso = 5.0v, vsx = 4.0v - - -100 a *6 lcd source driver low- level output current (binary output) i lob vso = 0.0v, vsx = 1.0v 100 - - a *6 lcd source driver delay t sd avdd = 5.5v gvdd = 5.0v sap = ? 001 ? - - tbd s *9 current consumption during standby mode istby standby mode, ta = 25 c - - - a *7 i vdd - tbd tbd a *8 current consumption during normal operation i vci no load, ta = 25 c - tbd tbd a *8 notes : 5. vgo is the output voltage of analog output pins g0 to g177. 6. vsx is the voltage applied to analog output pins s1 to s396. vso the output voltage of analog output pins s1 to s396 7. vdd3 = 3.0v, vdd = 2.0v, vci = 2.7v, vbs = vss and standby mode. 8. vdd3 = 3.0v, vdd = 2.0v, vci = 2.7v, vbs = vss, fosc = 177 khz(176 display line), internal register, nl[4:0] = ? 10101 ? , rtn[3:0] = ? 0000 ? , div[1:0] = ? 00 ? internal power registers, vc[2:0] = ? 011 ? , bt[2:0] = ? 010 ? , vrh[3:0] = ? 1100 ? , vrl[3:0] = ? 0110 ? vcm[4:0] = ? 10110 ? , vdv[4:0] = ? 10000 ?
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 106 ac characteristics table 42 . parallel write interface characteristics (68 mode , hwm = 0 ) ( vdd = 1.8v to 2.5v, t a = - 3 0 to +85 o c) vdd3 = 1.8v to 2.5v vdd3 = 2.6v to 3.3v characteristic symbol min. max . min. max . unit write t cycw68 600 - 250 c ycle time read t cycr68 800 500 pulse rise / fall time t r , t f - 25 25 write t w h w68 90 - 40 e pulse width high read t wh r68 350 250 write t w lw68 300 - 70 e pulse width low read t w lr68 400 200 rw, rs and csb setup time t as68 10 - 10 rw, rs and csb hold time t ah68 5 - 2 write data setup time t wds68 6 0 - 60 write data hold time t wdh68 15 - 2 read data delay time t rdd68 - 200 - 200 read data hold time t rdh68 5 5 ns table 43. parallel write interface characteristics (68 mode , hwm = 1 ) ( vdd = 1.8v to 2.5v, t a = - 3 0 to +85 o c) vdd3 = 1.8v to 2.5v vdd3 = 2.6v to 3.3v characteristic symbol min. max . min. max . unit write t cycw68 200 - 100 c ycle time read t cycr68 800 500 pulse rise / fall time t r , t f - 25 25 write t w h w68 90 - 40 e pulse width high read t wh r68 350 250 write t w lw68 9 0 - 40 e pulse width low read t w lr68 400 200 rw, rs and csb setup time t as68 10 - 10 rw, rs and csb hold time t ah68 5 - 2 write data setup time t wds68 6 0 - 60 write data hold time t wdh68 15 - 2 read data delay time t rdd68 200 200 read data hold time t rdh68 5 5 ns
S6D0110 132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd preliminary 107 table 44. parallel write interface characteristics ( 80 mode , hwm = 0 ) ( vdd = 1.8v to 2.5v, t a = - 3 0 to +85 o c) vdd3 = 1.8v to 2.5v vdd3 = 2.6v to 3.3v characteristic symbol min. max . min. max . unit write t cycw80 600 - 250 c ycle time read t cycr80 800 500 pulse rise / fall time t r , t f - 25 25 write t wlw80 90 - 40 p ulse width low read t w lr80 350 250 write t w hw80 300 - 70 p ulse width high read t w hr80 400 200 rw, rs and csb setup time t as80 10 - 10 rw, rs and csb hold time t ah80 5 - 2 write data setup time t wds80 6 0 - 60 write data hold time t wdh80 15 - 2 read data delay time t rdd80 - 200 - 200 read data hold time t rdh80 5 5 ns table 45. parallel write interface characteristics ( 80 mode , hwm = 1 ) ( vdd = 1.8v to 2.5v, t a = - 3 0 to +85 o c) vdd3 = 1.8v to 2.5v vdd3 = 2.6v to 3.3v characteristic symbol min. max . min. max . unit write t cycw80 200 - 100 c ycle time read t cycr80 800 500 pulse rise / fall time t r , t f - 25 25 write t wlw80 90 - 40 p ulse width low read t w lr80 350 250 write t w hw80 9 0 - 40 p ulse width high read t w hr80 400 200 rw, rs and csb setup time t as80 10 - 10 rw, rs and csb hold time t ah80 5 - 2 write data setup time t wds80 6 0 - 60 write data hold time t wdh80 15 - 2 read data delay time t rdd80 200 200 read data hold time t rdh80 5 5 ns
132 rgb source & 176 gate driver with internal ram for 65k colors tft-lcd s6d011 0 preliminary 108 table 46. clock synchronized serial write mode characteristic s ( vdd = 1.8v to 2.5v, t a = - 3 0 to +85 o c) vdd3 = 1.8v to 2.5v vdd3 = 2.6v to 3.3v characteristic symbol min. max . min. max . unit serial clock cycle time tscyc 0.1 20 0.1 20 us serial clock rise / fall time t r , t f - 20 20 ns pulse width high for write t schw 40 - 40 - ns pulse width high for read t schr 230 - 230 - ns pulse width low for write t sclw 6 0 - 60 - ns pulse width low for read t sclr 230 - 230 - ns chip select setup time t css 20 - 20 - ns chip select hold time t csh 60 - 60 - ns serial input data setup time t sids 30 - 30 - ns serial input data hold time t sidh 30 - 30 - ns serial output data delay time t sodd - 200 - 130 ns serial output data hold time t sodh 5 - 5 - ns table 46. reset timing characteristic s ( vdd = 1.8v to 2.5v, t a = - 3 0 to +85 o c) vdd3 = 1.8v to 2.5v vdd3 = 2.6v to 3.3v characteristic symbol min. max . min. max . unit reset low pulse width t res 1 - 1 - us

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